[show abstract][hide abstract] ABSTRACT: The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I - V characteristics and charge pumping measurements. The impact of stress on drain saturation current ( I <sub>dsat</sub>), threshold voltage ( Vt ), transconductance peak ( gm ), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases I <sub>dsat</sub> and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and I <sub>dsat</sub>, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of I <sub>dsat</sub>, Vt , gm , and SS under positive stress is more severe for devices with high- k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.
IEEE Transactions on Device and Materials Reliability 04/2011; · 1.52 Impact Factor
[show abstract][hide abstract] ABSTRACT: We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
[show abstract][hide abstract] ABSTRACT: We present a successfully implemented ESD design automation framework that evaluates and verifies the ESD protection methodology at all stages of a standard integrated circuit design flow. The tools used at each step of the flow and sample results showing excellent correlation to hardware test data is presented.
[show abstract][hide abstract] ABSTRACT: In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is needed to ensure maximum Vt1. The minimum and maximum Vt1 window for cascoded driver is shown to range between a single FET Vt1 and twice single FET Vt1.
[show abstract][hide abstract] ABSTRACT: Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (V<sub>BD</sub>) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the V<sub>BD</sub> of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the V<sub>BD</sub> from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ~100 ns to ~20 μs, suggesting that the failure mechanism remains the same as in the longer time scale.
[show abstract][hide abstract] ABSTRACT: We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, and demonstrate that all devices including analog, I/O, and passive devices can be fabricated in the thin silicon layer. Excellent device matching, g<sub>m</sub>/g<sub>ds</sub> scaling to small gate length, good RF performance, and absence of history effect are the main features of the ETSOI technology.
[show abstract][hide abstract] ABSTRACT: A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.
[show abstract][hide abstract] ABSTRACT: Overshoot voltages during VFTLP testing of DTSCRs are investigated. The DTSCRs in a 65 nm process turn on at approximately 500 ps. The overshoot voltages from DTSCRs are shown to cause gate oxide failures when gate oxide monitors were added in parallel to DTSCR ESD devices. Scaling trends show DTSCRs turning on at approximately 150 ps when technologies are scaled down to the 32 nm node.
[show abstract][hide abstract] ABSTRACT: Low current and high current ESD characteristics of the Poly-Bounded and High-k Metal Gate-bounded ESD diodes with varying stress components are studied in 32 nm SOI technology. It is observed that embedded SiGe (e-SiGe) stress on the anode degrades the ESD protection performance significantly mainly due to the introduction of defects in the active region. Compressive stress liners, tensile stress liners and stress due to Stress Memorization Technique (SMT) show only a marginal shift in the diode performance.
[show abstract][hide abstract] ABSTRACT: Technology scaling data are presented based on 65 nm, 45 nm, and the 32 nm high-K, metal gate process. Thin oxide NFET parasitic bipolar snapback and gate dielectrics breakdown voltages decrease to 3.2V and 3.6V, respectively. The top concern is to achieve adequate voltage clamping at I/O pads. Continuous improvement in ESD device failure currents per area is found. Vertical metal wiring schemes are needed to overcome wiring resistance challenges.
[show abstract][hide abstract] ABSTRACT: Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.
[show abstract][hide abstract] ABSTRACT: We report on the ESD performance of dual well and triple well, silicide-blocked stacked NMOSFETs in a 45 nm CMOS technology. Triple well stacked NMOSFETs have a 1.5X higher HBM failure voltages compared to dual well designs. Further, we report on the effect of gate-biasing on the ESD performance of dual well, gate-silicided, silicide-blocked 2.5 V stacked NMOSFETs. For gate voltages (V<sub>GS</sub>) larger than 40% of the drain voltage (V<sub>DS</sub>) under the transient ESD conditions, the HBM failure voltage decreases with increasing gate voltage when applied on top gate with bottom gate grounded.
[show abstract][hide abstract] ABSTRACT: S-parameter test structures from a 45 nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42 fF/mum, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65 fF/um for thin oxide devices, and ~0.72 fF/mum for thick oxide devices. Gate-Non-Silicided devices have ~20% higher capacitance because of increased junction area.
[show abstract][hide abstract] ABSTRACT: A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
[show abstract][hide abstract] ABSTRACT: Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V<sub>g</sub> = V<sub>d</sub>), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V<sub>g</sub> = V<sub>d</sub> at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V<sub>g</sub> = V<sub>d</sub> shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.
IEEE Electron Device Letters 04/2008; · 2.79 Impact Factor
[show abstract][hide abstract] ABSTRACT: Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices stressed under HCI conditions at room temperature show NBTI-like behavior at higher stress voltages and combined HCI-NBTI behavior at lower stress voltages. HS PMOS devices stressed under HCI conditions show a combined HCI and NBTI degradation behavior across the entire stress bias range. Both HS and I/O devices degrade more when HCI stressed with FB at high stress voltages; however the degradation becomes comparable to BC devices at lower stress voltages.
[show abstract][hide abstract] ABSTRACT: Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.
[show abstract][hide abstract] ABSTRACT: Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.
[show abstract][hide abstract] ABSTRACT: S-parameter test structures show total capacitances per perimeter of ESD diodes increased from ~0.42fF/mum in 90nm technologies to ~0.7fF/mum in 65nm and 45nm technologies. To achieve lower capacitances for high frequency circuits, layout and process optimization are needed. SCR devices from a 45nm technology show ~0.32fF/mum and can be used for circuit applications with stringent capacitance requirement. Two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.