N. Shen

Institute of Microelectronics, Tumasik, Singapore

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Publications (8)11.65 Total impact

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    ABSTRACT: This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality—wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current $( < \hbox{5}\ \hbox{pA}/\mu\hbox{m})$ and high $I_{\rm ON}/I_{\rm OFF}$ ratio $(> \hbox{10}^{6})$. Furthermore, we briefly discuss the implication of these devices in CMOS nand logic implementation.
    IEEE Electron Device Letters 02/2012; 33(2):152-154. DOI:10.1109/LED.2011.2176309 · 3.02 Impact Factor
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    ABSTRACT: For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.
    IEEE Electron Device Letters 12/2011; 32(11-32):1492 - 1494. DOI:10.1109/LED.2011.2165693 · 3.02 Impact Factor
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    ABSTRACT: Presented is a resistive, vertically oriented, silicon electromechanical cantilever switch, fabricated with a two-mask top-down CMOS-compatible process. The fabricated switch has a vertical height of approximately 500 nm, a tip width of 35 nm, and an airgap of 30 nm between the cantilever and two lateral gates. Preliminary testing results show an initial pull-in voltage of 17 V with contact held by van der Waals forces even in the absence of actuation voltage. Subsequent switching occurs at 25 V. With low-cost fabrication and high integration density, the vertical nanoelectromechanical (NEM) switch is a promising candidate for memory and computing applications.
    Electronics Letters 07/2011; 47(13-47):759 - 760. DOI:10.1049/el.2011.1073 · 1.07 Impact Factor
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    ABSTRACT: This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs) [2,3]. This paper discusses the basic idea of vertical slit device architecture, the physics of VeSFETs, their key electrical properties in comparison with trigate FinFETs, and shows experimental characteristics of fabricated devices.
    Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference; 07/2011
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    ABSTRACT: In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high I<sub>on</sub>/I<sub>off</sub> ratio of >; 10<sup>6</sup>, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced barrier lowering [(DIBL); ~50 mV/V] with a wire diameter of ~30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.
    IEEE Electron Device Letters 07/2011; 32(6-32):770 - 772. DOI:10.1109/LED.2011.2136315 · 3.02 Impact Factor
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    ABSTRACT: In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior by highlighting the features of the I-V and C-V characteristics, as well as the electrostatic potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.
    Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on; 04/2011
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    ABSTRACT: NanoElectroMecha nical (NEM) switches have been proposed for non-volatile memory applications, but low device density remains a key challenge for horizontal switches. This paper presents a resistive, vertically oriented NanoElectroMecha nical (NEM) nano-pillar cantilever switch made of mono-crystaline silicon, with a cell size of 8P2. Using a top-down CMOS-compatible process requiring two lithography masks, nano-pillar switches with a height of 500nm, tip thickness of 35nm, and 25nm air gap are fabricated. Device switching is performed using electrostatic actuation, while non-volatile memory function is achieved by maintaining switch contact with van der Waals forces after pull-in even when the actuating voltage is removed. Switching and non-volatile memory capabilities are demonstrated, with pull-in voltage Vpi = 17V and release voltage Vrelease = -25V. With low-cost fabrication process and high device density, the nano-pillar device is a promising candidate for non-volatile memory applications.