N. Shen

Nanyang Technological University, Singapore, Singapore

Are you N. Shen?

Claim your profile

Publications (10)13.68 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: For the first time, nano-meter-scaled 1T-1R non-volatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated. Transistors are fabricated using fully CMOS compatible technology and RRAM cells are stacked onto the tip of the nano-pillars (with a diameter down to ~37nm) to achieve a compact 4F2 footprint. In addition, through this platform, different RRAM stacks comprising CMOS friendly materials are studied, and it is found that TiN/Ni/HfO2/n+-Si RRAM cells show excellent switching properties in either bipolar or unipolar mode, including (1) ultra-low switching current/power: SET ~20nA/85nW and RESET ~200pA/700pW, (2) multi-level switchability, (3) good endurance, >105, (4) satisfactory retention, 10 years at 85oC; and (5) fast switching speed ~50ns. Moreover, this vertical (gate-all-around) GAA nano-pillar based 1T-1R architecture provides a more direct and flexible test vehicle to verify the scalability and functionality of RRAM candidates with a dimension close to actual application.
    Electron Devices Meeting (IEDM), 2012 IEEE International; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.
    Journal of Nanotechnology 01/2012; 2012.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Presented is a resistive, vertically oriented, silicon electromechanical cantilever switch, fabricated with a two-mask top-down CMOS-compatible process. The fabricated switch has a vertical height of approximately 500 nm, a tip width of 35 nm, and an airgap of 30 nm between the cantilever and two lateral gates. Preliminary testing results show an initial pull-in voltage of 17 V with contact held by van der Waals forces even in the absence of actuation voltage. Subsequent switching occurs at 25 V. With low-cost fabrication and high integration density, the vertical nanoelectromechanical (NEM) switch is a promising candidate for memory and computing applications.
    Electronics Letters 07/2011; · 1.04 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs) [2,3]. This paper discusses the basic idea of vertical slit device architecture, the physics of VeSFETs, their key electrical properties in comparison with trigate FinFETs, and shows experimental characteristics of fabricated devices.
    Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference; 07/2011
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high I<sub>on</sub>/I<sub>off</sub> ratio of >; 10<sup>6</sup>, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced barrier lowering [(DIBL); ~50 mV/V] with a wire diameter of ~30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.
    IEEE Electron Device Letters 07/2011; · 2.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior by highlighting the features of the I-V and C-V characteristics, as well as the electrostatic potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.
    Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on; 04/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: NanoElectroMecha nical (NEM) switches have been proposed for non-volatile memory applications, but low device density remains a key challenge for horizontal switches. This paper presents a resistive, vertically oriented NanoElectroMecha nical (NEM) nano-pillar cantilever switch made of mono-crystaline silicon, with a cell size of 8P2. Using a top-down CMOS-compatible process requiring two lithography masks, nano-pillar switches with a height of 500nm, tip thickness of 35nm, and 25nm air gap are fabricated. Device switching is performed using electrostatic actuation, while non-volatile memory function is achieved by maintaining switch contact with van der Waals forces after pull-in even when the actuating voltage is removed. Switching and non-volatile memory capabilities are demonstrated, with pull-in voltage Vpi = 17V and release voltage Vrelease = -25V. With low-cost fabrication process and high device density, the nano-pillar device is a promising candidate for non-volatile memory applications.
    01/2011;
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this letter, we demonstrate a multibit programmable vertical silicon nanowire (SiNW) SONOS memory using a top-down method. The flash devices realized on highly scaled squarish SiNW down to 20 nm in diagonal show much improved program/erase speed and window along with good retention and endurance characteristics as compared to the ones with a large dimension. The performance improvements with scaling of wire dimensions are attributed to the enhancement of the electric field in tunnel oxide and reduction in blocking oxide as a result of reduced radius of curvatures, particularly on the corners of the squarish wire.
    IEEE Electron Device Letters 06/2010; · 2.79 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this letter, we present the fabrication and characteristics of a gate-all-around SONOS Flash memory using a vertical Si nanowire (SiNW), which is proposed to be the key building block to realize the 3-D multilevel memory technology for ultrahigh-density application. A highly scaled SiNW with a diameter down to 50 nm using CMOS-compatible technology was achieved. Using an unoptimized SONOS gate stack (with the thickness of SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub>/SiO<sub>2</sub> ~ 5/5/6 nm), the devices exhibit well-behaved memory characteristics, in terms of program/erase window, retention, and endurance properties.
    IEEE Electron Device Letters 09/2009; · 2.79 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p<sup>+</sup>-i- n<sup>+</sup> tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent I <sub>on</sub> - I <sub>off</sub> ratio of ~ 10<sup>7</sup> with a low I <sub>off</sub> ( ~ 7 pA/mum). The obtained 53 muA/mum I <sub>on</sub> can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.
    IEEE Electron Device Letters 08/2009; · 2.79 Impact Factor