H.-B. Lee

Publications (2)0 Total impact

• Conference Proceeding: Voltage Ramp and Time-Dependent Dielectric Breakdown in Ultra-Narrow Cu/SiO2 Interconnects

  H. Park, H.-B. Lee, H.-K. Jung, Z.-S. Choi, J.-Y. Bae, J.-W. Hong, K.-I. Choi, B.-L. Park, E.-J. Lee, J.-W. Kim, J.-M. Lee, G.-H. Choi, J.-T. Moon
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  ABSTRACT: Voltage ramp dielectric breakdown (VRBD) and time-dependent dielectric breakdown (TDDB) characteristics of ~40nm-wide Cu/SiO 2 interconnect dielectrics were investigated. The addition of a SiH 4 treatment before capping SiN deposition led to more uniform breakdown fields, and better TDDB performance. The integration of a Ti-based barrier resulted in the best uniformity of breakdown fields, and a dramatic enhancement of TDDB reliability. The relationship between the VRBD and the TDDB characteristics was discussed, and the effect of SiH 4 treatment was analyzed using TEM.
  Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
• Conference Proceeding: A Highly Reliable Cu Interconnect Technology for Memory Device

  H.B. Lee, J.W. Hong, G.J. Seong, J.M. Lee, H. Park, J.M. Baek, K.I. Choi, B.L. Park, J.Y. Bae, G.H. Choi, S.T. Kim, U.I. Chung, J.T. Moon, J.H. Oh, J.H. Son, J.H. Jung, S. Hah, S.Y. Lee
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  ABSTRACT: This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.
  International Interconnect Technology Conference, IEEE 2007; 07/2007