-
Yan Li,
Seungpil Lee,
Yupin Fong, Feng Pan,
Tien-Chien Kuo,
Jongmin Park,
T. Samaddar,
Hao Thai Nguyen,
M.L. Mui,
K. Htoo, [......],
Liping Peng,
D. Das,
D. Ghosh,
V. Kalluru,
S. Kulkarni,
R.-A. Cernea,
S. Huynh,
D. Pantelakis,
Chi-Ming Wang,
K. Quader
[show abstract]
[hide abstract]
ABSTRACT: A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.
IEEE Journal of Solid-State Circuits 02/2009; · 3.23 Impact Factor
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R.-A. Cernea,
Long Pham,
F. Moogat,
Siu Chan,
Binh Le,
Yan Li,
Shouchang Tsao,
Tai-Yuan Tseng,
Khanh Nguyen,
J. Li, [......],
H. Mukai,
K. Kawakami,
C. Liang,
T. Ip,
Shu-Fen Chang,
J. Lakshmipathi,
S. Huynh,
D. Pantelakis,
M. Mofidi,
K. Quader
[show abstract]
[hide abstract]
ABSTRACT: A 16 Gb 4-state MLC NAND flash memory augments the sustained program throughput to 34 MB/s by fully exercising all the available cells along a selected word line and by using additional performance enhancement modes. The same chip operating as an 8 Gb SLC device guarantees over 60 MB/s programming throughput. The newly introduced all bit line (ABL) architecture has multiple advantages when higher performance is targeted and it was made possible by adopting the ldquocurrent sensingrdquo (as opposed to the mainstream ldquovoltage sensingrdquo) technique. The general chip architecture is presented in contrast to a state of the art conventional circuit and a double size data buffer is found to be necessary for the maximum parallelism attained. Further conceptual changes designed to counterbalance the area increase are presented, hierarchical column architecture being of foremost importance. Optimization of other circuits, such as the charge pump, is another example. Fast data access rate is essential, and ways of boosting it are described, including a new redundancy scheme. ABL contribution to energy saving is also acknowledged.
IEEE Journal of Solid-State Circuits 02/2009; · 3.23 Impact Factor
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Yan Li,
Seungpil Lee,
Yupin Fong, Feng Pan,
Tien-Chien Kuo,
Jong Park,
T. Samaddar,
Hao Nguyen,
Man Mui,
Khin Htoo, [......],
Liping Peng,
D. Das,
D. Ghosh,
V. Kalluru,
S. Kulkarni,
R. Cernea,
S. Huynh,
D. Pantelakis,
Chi-Ming Wang,
K. Quader
[show abstract]
[hide abstract]
ABSTRACT: We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm<sup>2</sup> compared to 0.079 Gb/mm<sup>2</sup> on D2 chips, as previously reported (K. Takeuchi et al.,2006). This is a 41% improvement in Gb/mm<sup>2</sup> and a 20% gain in overall die-size.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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R. Cernea,
Long Pham,
Farookh Moogat,
Siu Chan,
Binh Le,
Yan Li,
Shouchang Tsao,
Tai-Yuan Tseng,
Khanh Nguyen,
J. Li, [......],
H. Mukai,
K. Kawakamr,
C. Liang,
T. Ip,
Shu-Fen Chang,
J. Lakshmipathi,
S. Huynh,
D. Pantelakis,
M. Mofidi,
K. Quader
[show abstract]
[hide abstract]
ABSTRACT: In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for actual operations, every other cell along a selected word line (WL) (Takeuchi, 2006), this design simultaneously exercises them all. A performance improvement of at least 100% is derived from this all-bitline (ABL) architecture relative to conventional chips. Additional techniques push performance to even higher levels.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
