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Publications (3)1.92 Total impact

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    ABSTRACT: Practical selectivity window of selective epitaxial growth (SEG) using a H2/SiH4/Cl2 cyclic chemical vapor deposition (CVD) system has been investigated with the batch-type vertical furnace equipment, replacing a conventional single-wafer H2/dichlorosilane/HCl CVD system. The process temperature was less than 700 °C, which is suitable for a low thermal budget process applicable to next-generation memories including vertical pn-diode switches. Selectivity loss is quantified by an in-line inspection tool to determine the practical number of selectivity losses. The H2/SiH4/Cl2 cyclic CVD system provides an excellent capacity of 40 wafers per batch. Selectivity loss, which is one of the most crucial features in the SEG process for the diode application, is controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and the practical number of selectivity loss is confirmed to be less than 100 in 200 mm wafers. Without high temperature annealing in hydrogen ambient, low temperature cyclic SEG in the batch reactor ensures the clean interface and improved crystalline quality of SEG-Si, as well as high throughput.
    Semiconductor Science and Technology 03/2011; 26(5):055022. · 1.92 Impact Factor
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    ABSTRACT: We have proposed an integrated method to realize MLC PRAM at 45 nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.
    VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
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    ABSTRACT: A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F<sup>2</sup>. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.
    VLSI Technology (VLSIT), 2010 Symposium on; 07/2010