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ABSTRACT: Successful implementation of 3D integration technology requires understanding of the unique yield and reliability issues associated with through-silicon vias (TSVs), with adequate design and process considerations to address these issues. This paper relates to the characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs designed for use in 3D Si interposers and 3D wafer-level packaging applications. The paper will describe a variety of methods for characterization of Cu TSV fill quality, microstructure, and thermally-induced TSV height increase known as “copper protrusion” or “copper pumping.” An X-ray imaging method was used for fast, nondestructive analysis of Cu TSV plating profiles and detection of trapped voids. In addition, a plasma focused ion beam (plasma-FIB) process was used to generate high quality cross sections of full TSVs, 50μm in diameter and 150μm depth. Imaging of TSVs by Ga FIB channeling contrast and electron backscattered diffraction (EBSD) provided information about Cu microstructure, including quantitative analysis of grain size. It was observed that TSVs exposed to elevated temperatures exhibited a substantial increase in grain size, which was associated with the Cu protrusion effect. This paper will also report the results of TSV integration with subsequent layers, with analysis of thermo-mechanical failures due to interactions between Cu TSVs and adjacent dielectric layers. The use of an anneal step to stabilize the plated Cu TSVs, prior to build-up of subsequent dielectric layers, will be described.
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st; 07/2011
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ABSTRACT: The through-silicon via is a key element in the development of 3D integration technology for new generations of advanced electronic systems. There are several challenges associated with filling these deep, relatively large diameter vias using standard copper electroplating processes, like those common in damascene technology. This paper will summarize a process development for copper electroplating of deep silicon vias in the range of 20-200 mum in diameter and 150-375 mum in depth. The test vias had aspect ratios ranging from 1.3:1 to 8:1, with sidewalls which were approximately vertical. The paper will discuss copper via plating results with respect to additive component levels, current density, seed layer quality, and sample pretreatments pertaining to wetting of the vias in the plating solution.
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th; 06/2009
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ABSTRACT: The paper describes a platform technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator devices hybridized with Si electronics. Among these applications are high performance infrared focal plane array detectors
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: This paper describes a technology platform being developed for three-dimensional (3-D) integration of thin stacked silicon integrated circuits (ICs). 3-D integration technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator array devices hybridized with silicon read-out electronics. Currently, advanced 3-D integrated infrared focal plane array detectors are being developed within the DARPA vertically integrated sensor arrays (VISA) program. Here, we describe the 3-D integration process flow and demonstrations developed in the VISA program
Electronic Components and Technology Conference, 2006. Proceedings. 56th;
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ABSTRACT: This paper describes a technology platform being developed for three-dimensional (3-D) integration of thin stacked silicon integrated circuits (ICs). 3-D integration technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator array devices hybridized with silicon read-out electronics. Currently, advanced 3-D integrated infrared focal plane array detectors are being developed within the DARPA Vertically Integrated Sensor Arrays (VISA) program. Here, we will describe the 3-D integration process flow and demonstrations developed in the VISA program.
