Jose A. Villasante-Bembibre

Universitat Ramon Llull, Barcino, Catalonia, Spain

Are you Jose A. Villasante-Bembibre?

Claim your profile

Publications (3)0 Total impact

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper introduces two applications of Discrete Time Cellular Non-Linear Networks (DTCNN) in a robot guiding avoiding obstacles algorithm and prove the feasibility of both applications: a high data rate one, using a CMOS camera, and small data rate one, using ultrasonic sensors. The key value of DTCNNs is the locally connections and the parallelism in processing. These characteristics permit a hardware implementation, in our case over a Field Programmable Gate Arraw (FPGA) and a real time template based algorithm processing. A camera and an ultrasonic sensor are used as avoiding obstacles system, requiring both implementations, different inputs informations: the first one complex environment information and the later for basic situations information where impulsive response is required. Both input can have an enhanced behaviour within DTCNN structure.
    Neural Networks (IJCNN), The 2010 International Joint Conference on; 08/2010
  • J. Albo-Canals · J. A. Villasante-Bembibre · J. Riera-Babures · X. Vilasis-Cardona
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split & Shift techniques to have a 12 �? 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I2C interfece to communicate with Lego Mindstorm Device.
  • J. Albo-Canals · Jose A. Villasante-Bembibre · Jordi Riera-Babures · N.A. Fernandez-Garcia · V.M. Brea
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an 8-bit FPGA implementation of a discrete time cellular neural network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 31 times 31 grid that processes more than 2500 images per second. As this work evolves from a previous binary DTCNN implementation, results are compared in terms of area occupancy, routing complexity and processing time. Several design techniques have been applied to optimize the VHDL implementation on an Altera Stratix II-EP2S60F484C5 FPGA device. Moreover, as technology independent description allows easy migration to other devices or vendors, the benefits of FPGA technology evolution are discussed, focusing on DTCNN implementations.
    Circuit Theory and Design, 2009. ECCTD 2009. European Conference on; 09/2009