Young-Ho Kwak

Korea University, Sŏul, Seoul, South Korea

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Publications (16)16.52 Total impact

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    ABSTRACT: This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2013; 60(2):268-278. · 2.24 Impact Factor
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    ABSTRACT: A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(11):2080-2093. · 1.22 Impact Factor
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    ABSTRACT: This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2013; 60(2):303-313. · 2.24 Impact Factor
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    ABSTRACT: A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH $\Delta \Sigma$ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of $\pm 0.5\%$ to 3.5% in steps of 0.5% and three modulation frequencies of $f _{\rm m}$, $2 f _{\rm m}$ and $3 f _{\rm m}$. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 ${\hbox{mm}}^{2}$ in a 0.13-$\mu{\hbox{m}}$ CMOS process and consuming 23.72 mW at 3.5 GHz.
    IEEE Journal of Solid-State Circuits 01/2012; 47(5):1199-1208. · 3.06 Impact Factor
  • IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 02/2011
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    ABSTRACT: generators, PG1 and PG2 make five control signals respectively. FVC1 and FVC2 convert the frequency information to voltage, VFVC1 and VFVC2, respectively. The charge pump (CP) generates VCTRL from the difference of these two voltages. The loop filter comprises a capacitor of tens of picofarad, sufficient to secure stability [6] and occupying a small area. DAC1 and DAC2 connect an interface between analog FLL and DSSC for frequency modulation. The Newton-Raphson profile generator produces a nonlinear profile with various modulation frequencies of fm, 2fm and 3fm. The 1-1-1 MASH ΔΣM transfers the modulation profile to the δ controller. The δ controller decodes the output of ΔΣM, DSM[3:0] and expands the control signal to control the spreading direction of up and down and spreading ratio (±0.5 to 3.5% with Δ=0.5%) of the output clock CLKOUT. Figure 20.8.2 shows the schematic of the proposed frequency modulation technique that uses a double binary-weighted DAC and FVC. The FVC detects the frequency with current source IM1 and the S/H circuit. The current source charges C1, and during the charge sharing period, C2 follows the sampling voltage level of C1 and finally output voltage is settled to IM1/(C1f), where f is the frequency of CLKFDIV. If IM1 can be modulated with the DAC, the VCO output frequency can also be modulated. The double binary-weighted DAC has eight groups of current cells and 172 always-turned-on current cells. Each group has binary-weighted current cells but also seven groups, 1×G0, 2×G1 and 4×G2, except for a dotted line group that are built up as a binary-weight. Thus, it is possible to have seven current levels for the ΔΣ modulation and seven current step differences for the multiple δ. Each current cell has the same amount of current, IUNIT, with bias voltage VBN. When the SSCG operates with δ=-3.5%, SEL2[8:0] modulates the current of DAC2 from 172IUNIT to 221IUNIT with a step of 7IUNIT. Then, the SEL1[8:0] and SEL1_UP[2:0] fix the DAC1 current to 200IUNIT, hence 193/2001=-3.5% of down spreading with 1-1-1 MASH ΔΣM is achieved. In the case of up spreading, δ=+3.5%, SEL2_UP[2:0] increases the DAC2 current by 7IUNIT so that 207/200-1=+3.5% of up spreading can also be achieved. The op-amp A1 is used in the CP for more precise matching of sink and source currents.
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 01/2011;
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    ABSTRACT: A multi-port serial link with wide-range CDR using digital vernier phase shifting and dual-mode control is presented. The proposed vernier phase shifter generates finely-spaced phase steps and provides unlimited phase rotating with a 13.34-ps phase step at 5 Gbps. By inherently digital nature, the vernier phase shifter enables semi-digital dual-loop CDR with precise tracking performance, and with the dual-mode control, the proposed CDR extends the operating range from 250 Mbps to 5 Gbps and achieves a BER of less than 10 at 5 Gbps with 2 1P RBS. Fabricated in a 0.13- mC MOS process, the main PLL and the single receiver dissipate 9.0 mW and 19.2 mW respectively at 5 Gbps from a 1.2 V supply.
    IEEE Journal of Solid-State Circuits 01/2011; 46(11):2560-2570. · 3.06 Impact Factor
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    ABSTRACT: A multi-port serial link with a wide-range CDR using digital Vernier phase shifting and dual mode control is presented. The proposed Vernier phase shifter generates fine-resolution phase steps and provides unlimited phase rotating. With the dual mode control, the proposed CDR extends the operating range from 250Mbps to 5Gbps. The proposed CDR provides 13.34ps phase steps at 5Gbps and achieves a BER of less than 10<sup>-12</sup> for the range of 250Mbps to 5Gbps. Fabricated in a 0.13-μm CMOS process, the proposed CDR dissipates 19.2mW at 5Gbps from a 1.2-V supply.
    Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian; 12/2010
  • Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
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    ABSTRACT: This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-¿m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 03/2010; · 1.33 Impact Factor
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    ABSTRACT: An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
    01/2010;
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    ABSTRACT: An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65 nm CMOS process burns 17 mW and occupies 0.4 mm2. The measured jitters are 1.1 nspp and 223.6 psrms, respectively with a multiplication factor of 1,024.
    IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings; 01/2009
  • Source
    Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
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    ABSTRACT: A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1V/ns to 3.6V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18um CMOS process, and the control block consumes 13.7mW at 1Gbps.
    Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008; 01/2008
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    ABSTRACT: This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full swing of internal nodes. Also, the power consumption of the proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E×D by 45.5% over ep-SFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.
    Electrical Engineering 04/2007; 89(5):371-375. · 0.30 Impact Factor
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    ABSTRACT: A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18mum CMOS process, the control block of the proposed driver occupies 0.009mm<sup>2</sup> and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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    ABSTRACT: A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm<sup>2</sup> and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz
    IEEE Journal of Solid-State Circuits 10/2006; · 3.06 Impact Factor
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    ABSTRACT: A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35 μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6ps<sub>pp</sub> at 1.3GHz.
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005