[Show abstract][Hide abstract] ABSTRACT: We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.
[Show abstract][Hide abstract] ABSTRACT: 3D-MAPS is a test vehicle for evaluating the architectural im-plications of microprocessors designed using 3D integration technology. The 3D-MAPS processor is a five-layer stack con-sisting of logic, cache, and DRAM layers. Testing such a 3D design presents several unique challenges. Our test architec-ture is a custom design, borrowing from the IEEE 1149.1 and 1500 standards. The design goals were to minimize pin count, maximize graceful degradation, and ensure complete diagnos-tic capability of the chip.