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ABSTRACT: Sun's T2 processor transition test methodology, verification and silicon debug are described. We illustrate our test mechanism, test sequence, test development, and the verification of this mechanism in silicon. Methods to identify slow flops, diagnose gate dominated paths, excite long delay for wire dominated paths, and find essential patterns for speed characterization are presented. In addition, a method is developed for recovering devices with a fewer good processor cores. All these applications together make transition test a much more powerful tool.
Test Conference, 2008. ITC 2008. IEEE International; 11/2008