Stefano Aresu

Infineon Technologies, München, Bavaria, Germany

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Publications (17)11.58 Total impact

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    ABSTRACT: Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS = −60 V, VGS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.
    Microelectronics Reliability 09/2014; 54(9-10):1883-1886. DOI:10.1016/j.microrel.2014.07.048 · 1.43 Impact Factor
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    ABSTRACT: A new generation of embedded-power technologies offering high performance LDMOSFETs was introduced and particularly the reliability of the devices were characterized. The combination of a 120nm logic process with LDMOS with thin gate oxide enables high efficiency power converters on small die sizes. The reliability of the new LDMOS transistors had to be optimized very accurately to achieve both reliable products and the new RON benchmark.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
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    ABSTRACT: The physical origin of both Negative- and Positive Bias Temperature Instability (N-/PBTI) is still unclear and under debate. We analyzed the rarely studied recovery behavior after PBTI stress in pMOSFETs and compared it with NBTI data obtained from the same technology. While recovery after short stress times is consistent with the previously reported emission of trapped holes, for stress times larger than 10 ks we observe an unusual recovery behavior not reported before. There, the device degradation appears to continue during recovery up to approximately 30 s. Only after that time “normal” recovery behavior dominates. We thoroughly analyze this new observation as this may have significant consequences regarding our understanding of both PBTI and NBTI.
    Microelectronics Reliability 09/2012; 52(s 9–10):1891–1894. DOI:10.1016/j.microrel.2012.06.015 · 1.43 Impact Factor
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    ABSTRACT: Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
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    ABSTRACT: Short term threshold instabilities may cause erratic behavior in analog circuits like comparators and analog-to-digital-converters. As conventional characterization procedures have not been appropriately sensitized to such issues, this kind of erratic behavior usually only occurs in products where it is very difficult to identify. Therefore, for example prior to the introduction of a new gate stack, it is essential to do a careful experimental characterization of short term threshold instabilities, which goes beyond standard NBTI or PBTI measurements. A reliable forecast of the effect of threshold instabilities on the performance of analog circuits will require circuit simulations taking the threshold instabilities into account.
    Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International; 01/2012
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    ABSTRACT: In the development of MOSFETs first 'Hot Carrier Injection' (HCI) played an important role for reliability aspects [1,2]. With new shrinked process generations and nitrided gate oxides additionally the 'Bias Temperature Instability' (BTI) raised and became the most critical mechanism. Some publications even claim that HCI is negligible in main-stream applications [3-6]. But is this statement generally true or is it the result of a partial view? This paper will discuss the area of conflict regarding the importance of N/PBTI and HCI. Some typical examples will illuminate different fields of applications with one dominating damage mechanism. Specific characteristics of these circuits and operation conditions leading to an outbalance of HCI or Negative-/Positive-BTI will be carved out. Finally it will be evaluated if a general trend is observable.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
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    ABSTRACT: Negative Bias Temperature Instability (NBTI) of pMOSFETs is nowadays the most prominent device degradation mechanism reported in the literature and a limiting factor for CMOS technology scaling. In contrast, for Positive Bias Temperature Instability (PBTI) of pMOSFET only very few publications can be found [1–4]. Most of the PBTI work is done for nMOSFETs from process nodes employing high-K dielectrics and not for pMOSFETs with silicon oxide dielectrics. Especially product related degradation based on application conditions leading to PBTI of pMOSFETs are not investigated satisfactorily. Furthermore an in-depth comparison of the impact on extrapolated product lifetime of NBTI, PBTI and the effect of NBTI & PBTI stress in sequence is missing.
    01/2011; DOI:10.1109/IIRW.2011.6142576
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    ABSTRACT: Hot-carrier, inducing source-drain current (IDS) increase in high-voltage p-channel lateral DMOS (LDMOS) transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), electrons are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel towards the source side (Figure 1). The source drain current (Ids) increase leads to threshold voltage shift (Vth→0V) and for higher stress conditions a drain-source leakage can be observed. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at low temperature is reported.
    01/2011; DOI:10.1109/IIRW.2011.6142593
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    ABSTRACT: In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.
    01/2011; DOI:10.1109/ISPSD.2011.5890780
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    ABSTRACT: Negative bias temperature instability (NBTI) degra-dation and recovery have been investigated for 7–50-nm non-nitrided oxides and compared to thin 1.8-and 2.2-nm nitrided oxides from a dual work function technology. A wide regime of stress fields from 2.5 to 10 MV/cm has been covered. Thermal activation has been studied for temperatures from 25 • C to 200 • C. The NBTI effect for the nitrided oxide is larger than for non-nitrided oxides. The percentage of threshold shift ΔV th which is "lost" during a long measurement delay—which is the quantity leading to curved ΔV th versus stress-time curves and to errors in extrapolated lifetimes—is about equal for nitrided or thick non-nitrided oxides. The fraction of recovered ΔV th is strongly dependent on stress time but only weakly dependent on stress field. Recovery in thick oxides leads to exactly the same problems as for non-nitrided oxides, and clearly, a fast measurement method is needed. The effect of short-term threshold shifts has been studied for extremely short stress times down to 200 ns. Index Terms—MOSFET, negative bias temperature instability (NBTI), recovery, relaxation.
    IEEE Transactions on Device and Materials Reliability 06/2009; 9. DOI:10.1109/TDMR.2009.2021389 · 1.54 Impact Factor
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    ABSTRACT: This work demonstrates that NBTI assessment by fast wafer level reliability methods is possible in a quantitative manner. This involves excluding time periods from the stress time that are used for restoration of damage recovered during stress interruption and a calibrated back extrapolation of measured recovery traces to short delay times based on the universal recovery equation. The development of the methodology, the challenges and the verification of the implemented algorithm are presented.
    01/2009; DOI:10.1109/IRPS.2009.5173395
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    ABSTRACT: NBTI degradation and recovery have been investigated for 7 to 50nm oxides and compared to a thin 2.2nm nitrided oxide. A wide regime of stress fields 2.5MV/cm to 8MV/cm has been covered. NBTI effect for the nitrided oxide is larger than for non-nitrided oxides. The percentage of threshold shift DeltaVth which is "lost" during a long measurement delay - which is the quantity leading to curved DeltaVth vs stress-time curves and to errors in extrapolated lifetimes - is about equal for nitrided or thick non-nitrided oxides. The fraction of recovered DeltaVth is strongly dependent on stress time but only weakly dependent on stress field. Recovery in thick oxides leads to exactly the same problems as for non-nitrided oxides and clearly a fast measurement method is needed.
    Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International; 11/2008
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    ABSTRACT: Bipolar transistors are part of the design manuals of almost all semiconductor wafer technologies. These design library devices must be qualified and released according to the present qualification standards, e.g. AEC (automotive electronic council) or JEDEC [Automotive Electronic Council. AEC-Q100-Rev-F; 2003; Automotive Electronic Council. AEC-Q101-Rev-C; 2005; JEDEC JP-001. Foundry process qualification guideline; 2002]. Dedicated stress tests (e.g. high temperature electrical operation (HTEO), bias temperature stress (BTS) or emitter base reverse bias (EBRB)) must be performed to check device specific drift and degradation mechanisms. A lifetime prediction must be performed on base of the determined device parameter drifts.The mentioned qualifications tests are arranged at typical device application conditions for electrical operation and temperature. Due to the breakdown behaviour of bipolar transistors the electrical operation parameters are limited to the save-operation-area (SOA). This excludes the possibility of any acceleration during these tests. Based on this fact the final check of the requested device lifetime in customer applications can be performed only by non-accelerated end-of-life tests.The paper shows a review of typical stress tests of dedicated bipolar transistors of an automotive power wafer technology. A presentation of the drift behaviour of the current gain (beta) parameter as function of stress time and qualification test is presented. In order to replace the end-of-life test requirement and to find a new approach to estimate the expected lifetime in the final device application a power law fitting procedure will be introduced. New aspects to discuss these results with respect to the defined lifetime target will be shown.
    Microelectronics Reliability 08/2008; 48(8-9):1509-1512. DOI:10.1016/j.microrel.2008.07.010 · 1.43 Impact Factor
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    ABSTRACT: Lower threshold voltage shift due to relaxation effect is known to occur after negative bias high temperature stress of MOS transistors. This relaxation happens on timescales shorter than those used for either wafer level or package level characterization. This may result in too optimistic lifetime estimates. Therefore, new methodologies for lifetime prediction demand new NBTI measurement techniques in Smart Power Technologies. In this work we will show positive aspects and weaknesses of the on-the-fly technique and under which conditions the method may still lead to consistent results.
    Microelectronics Reliability 08/2008; 48:1310-1312. DOI:10.1016/j.microrel.2008.07.015 · 1.43 Impact Factor
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    ABSTRACT: Experience shows that chip package interaction is a dominant cause for failures of electronic components. Optimising the technology by applying the standard temperature cycling test to detect these failures is very time consuming and not any more compatible with today’s development cycles.Early failure indicators (preferable electrically measurable) could be the key element to reduce the test effort and to guarantee the performance in an application.From the package point of view there are three main drivers to be taken into consideration: The temperature, i.e. all degradation processes with an activation energy, temperature swings, which cause thermo-mechanical stress due to different CTE (coefficient of thermal expansion) of the variety of different materials used for the assembly, and temperature gradients, especially when active cycles are applied (switching of the device) can lead to metal reconstruction and plastic deformation, reducing lifetime of the component drastically. Knowledge of the weak areas allows choosing the best test in order to make the addressed failure mode observable in the shortest time.This paper provides a decision basis to speed up technology qualification by using TS (thermal shock) instead of TC (thermal cycling). Results will be shown for different die attach materials.
    Microelectronics Reliability 08/2008; 48(8-9):1490-1493. DOI:10.1016/j.microrel.2008.07.034 · 1.43 Impact Factor
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    ABSTRACT: ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime.All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002].The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress.The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.
    Microelectronics Reliability 09/2007; 47:1512-1516. DOI:10.1016/j.microrel.2007.07.042 · 1.43 Impact Factor
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    ABSTRACT: In some automotive applications, high negative bias is used to faster switch off n-type devices. This exceptional operative gate voltage at relative high temperature can induce instability of device parameters (e.g. threshold voltage, transconductance, saturation current, etc.In this work we will show that positive charge trapping generated under exceptional negative bias can induce large threshold voltage shift. Even if the effect can partially recover during the standard operative condition, nevertheless large Vth, shift are still present and can affect the correct functionality of the device.
    Microelectronics Reliability 09/2007; 47:1416-1418. DOI:10.1016/j.microrel.2007.07.021 · 1.43 Impact Factor