[Show abstract][Hide abstract] ABSTRACT: An 18Mb DRAM has been designed in a 3.3-V, 0.5-µm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1Mb × 18 for optimization of wafer screen tests, while 3.3-V or 5.0-V operation is selected by choosing one of two M2 configurations. Selection of 2Mb × 9 or 1Mb × 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1Mb × 16 operation with 2Mb × 8, 4 Mb × 4, and 4Mb × 4 with any 4Mb independently selectable (4Mb × 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.
Ibm Journal of Research and Development 02/1995; 39(1.2-39):51 - 62. DOI:10.1147/rd.391.0051 · 0.69 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.