C. Shea

Publications (2)0 Total impact

• Conference Proceeding: Impact of Epi-Si growth temperature on Ge-pFET performance

  J. Mitard, K. Martens, B. DeJaeger, J. Franco, C. Shea, C. Plourde, F.E. Leys, R. Loo, G. Hellings, G. Eneman, Wei-E Wang, J.C. Lin, B. Kaczer, K. DeMeyer, T. Hoffmann, S. DeGendt, M. Caymax, M. Meuris, M.M. Heyns
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  ABSTRACT: In this study, we report a direct comparison between two epitaxial silicon processes: 500degC using SiH₄ and 350degC using Si₃H₈. Following four different metrics, we demonstrate that the reduction of silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO₂interface. However, the Epi Si growth at 350degC with Si₃H₈ remains beneficial compared to a growth performed at 500degC-SiH₄ especially when thin EOT Ge pFETs are targeted.
  Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
• Conference Proceeding: Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI

  J. Mitard, C. Shea, B. DeJaeger, A. Pristera, G. Wang, M. Houssa, G. Eneman, G. Hellings, W.E. Wang, J.C. Lin, F.E. Leys, R. Loo, G. Winderickx, E. Vrancken, A. Stesmans, K. DeMeyer, M. Caymax, L. Pantisano, M. Meuris, M. Heyns
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  ABSTRACT: For the first time, an STI module is integrated in an advanced 70 nm Ge-pFET technology allowing EOT scaling down to 0.85 nm. Gate leakage is kept below 0.2A/cm² and ION is increased inversely proportional to the EOT. The impact of this aggressive EOT scaling on hole mobility is also investigated by temperature measurements down to 4 K, suggesting the presence of defects at different levels of the Si/SiO₂/HfO₂ gate stack.
  VLSI Technology, 2009 Symposium on; 07/2009