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J. Mitard,
L. Witters, M.G. Bardon,
P. Christie,
J. Franco,
A. Mercha,
P. Magnone,
M. Alioto,
F. Crupi,
L.-A. Ragnarsson,
A. Hikavyy,
B. Vincent,
T. Chiarella,
R. Loo,
J. Tseng,
S. Yamaguchi,
S. Takeoka,
W.-E. Wang,
P. Absil,
T. Hoffmann
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ABSTRACT: This work demonstrates the successful integration of 0.85nm-EOT Si<sub>0.45</sub>Ge<sub>0.55</sub>-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si<sub>0.55</sub>Ge<sub>0.45</sub>-pFETs, an I<sub>ON</sub> of 630μA/μm at L<sub>G_POLY</sub> = 35nm with I<sub>OFF</sub> = 100nA/μm and V<sub>DD</sub> = -1V has been achieved without any epi-S/D boosters. Significant improvements at lower V<sub>DD</sub> have also been confirmed through complex circuit simulations and validated by experimental results.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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ABSTRACT: This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO<sub>2</sub> and high-¿ dielectrics by comparison to 2-D finite-element simulations.
IEEE Transactions on Electron Devices 05/2010; · 2.32 Impact Factor
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ABSTRACT: Suspended gate field-effect transistors (SG-FETs) with switching gates are interesting as digital logic switches because of their high I <sub>on</sub>/ I <sub>off</sub> current ratio and their infinite subthreshold slope. However, the limits of scalability of the SG-FETs are still unclear. This paper investigates two effects that could limit scaling: the dielectric charging and the dielectric roughness. To do so, a surface-potential-based model for suspended gate transistors with a mechanically switching gate is presented and validated using experimental data. Devices fabricated in a standard complimentary metal-oxide-semiconductor process are used for the model assessment. The model reproduces the effect of a fixed charge and the effect of a nonideal contact of the gate after pull-in. We show that, at the device dimensions required to follow the International Technology Roadmap for Semiconductors, these effects will be critical.
IEEE Transactions on Electron Devices 05/2010; · 2.32 Impact Factor
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ABSTRACT: Single-transistor floating-body RAM (FB-RAM) cells present a promising alternative for scalable high-density storage since both access and storage elements are implemented using a single FET-based device. Unlike embedded dynamic RAM (eDRAM) technology, the concept is fully scalable with decreasing technology nodes. However, to make the concept truly usable, special biasing conditions of the device need to be considered; hence, the peripheral elements must be designed accordingly. We propose an approach of FinFET-based cell and peripheral circuit to provide compatible bias conditions for efficient write-read and hold conditions. The periphery is based on the synchronized bit line and word line driver schemes capable of providing compatible voltages to the selected and unselected lines during the different operations. The full circuit has been validated, and the concept has been demonstrated by simulations using the silicon-proven model cards and design decks.
Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2010; · 1.41 Impact Factor
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ABSTRACT: Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because the voltages applied to access one cell can disturb the state of other cells. We propose an approach at circuit level to provide compatible bias conditions and to explore further on the optimization of the biasing voltages for improved write and read operations and improved retention. To do so we use synchronized bitline and wordline drivers providing different voltages to selected and unselected lines during the different operations. In addition, a robust sensing scheme is described that can be implemented in the same process technology as the array. The full circuit has been validated by simulations based on the experimental data of fabricated bulk FinFETs floating body cells and the design has been taped out.
Memory Technology, Design, and Testing, 2009. MTDT '09. IEEE International Workshop on; 10/2009
