K. Kaviani,
T. Wu,
A. Amirkhany,
J. Wei,
J. Shen,
C. Chen, T. Chin,
W. Beyene,
D. Dressler,
V. Gadde, [......],
D. Secker,
X. Shi,
F. Shuaeb,
S. Srinivas,
C. Tran,
A. Vaidyanath,
K. Vyas,
M. Jain,
K. Chang,
C. Yuan
[show abstract]
[hide abstract]
ABSTRACT: An improved asymmetric bidirectional memory interface implemented in 40-nm CMOS process achieves 20 Gbps per data link, and can also communicate with DDR3 and GDDR5 DRAM at 1.6 Gbps and 6.4 Gbps, respectively. The low-power tri-modal high-speed interface is enabled by a continuous 1.6 GHz to 10 GHz clock generation mechanism, and substantial reuse of the circuit elements between the signaling modes, particularly at the driver output stage. In the high speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE to the memory, while in memory READ it uses a linear equalizer (LEQ) with 3dB of peaking as well as a calibrated 1-tap predictive decision feedback equalizer (prDFE). The interface consisting of 16 data links achieves efficiency of better than 5.3 mW/Gbps.
VLSI Circuits (VLSIC), 2011 Symposium on; 07/2011
