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ABSTRACT: In this paper, we present an hardware implementation of spiking neural networks based on analog integrated circuits. These ICs compute in real-time a biologically realistic neuron models. Each integrated circuit includes five neurons and analog memory cells to set and store the conductance model parameters, and eventually optimize it to compensate the analog circuit variability. The circuits are embedded in a multi-board system all connected to a backplane with daisy-chain facilities. Each action potential computed by analog neuromimetic chips is time-stamped when detected by digital device (FPGA). These FPGAs are also in charge of the real-time plasticity computation and of controlling inter-boards communication. The implemented neural plasticity is also biological relevant thanks to its time dependent computation. The whole system is designed to compute programmable models and connectivity schemes.
Neural Networks (IJCNN), The 2010 International Joint Conference on; 08/2010
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ABSTRACT: In this paper, we present a multi-board system based on analog neuromimetic ICs. These ICs compute in realtime conductance-based models. These models are implemented in a modular architecture based on our analog IPs. Each IC includes five neurons and analog memory cells to set and store the conductance model parameters, and eventually optimize it to compensate the analog circuit variability. The circuits are embedded in a multi-board system able to host up to 120 neurons spread across 6 boards all connected to a backplane with daisy-chain facilities. Each action potential computed by analog neuromimetic chips is time-stamped when detected by digital device (FPGA). These FPGAs are also in charge of the real-time plasticity computation and of controlling inter-boards communication. The system is designed to compute programmable models and connectivity schemes.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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ABSTRACT: Large-scale spiking neural networks (SNN) are generally run on distributed and parallel architectures with multiple computation nodes. These architectures induce extra delays due to the node-to-node communication process. In multiboard & multichip SNNs, important delays may affect spike arrival time and, thus, can alter simulation results. In this work, we propose a method aiming to guarantee spike arrival time with arbitrary prefixed deadlines. The communication architecture is based on the token-passing access policy to grant access to shared communication channels. We show that several network parameters must be set carefully if spikes have to meet their deadlines. Parameters are chosen by taking into account the communication channel bandwidth, the arbitrary deadlines and the worst case situation that can happen in generating neural activity in SNNs. As proof of concept, we have built a system that emulates up to 120 analog Hodgkin-Huxley neurons spread across 6 boards. Experimental results show that whatever it happens (unless there is a network fault), spikes reach their destination with a maximum delay of 5 microseconds.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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ABSTRACT: Synaptic plasticity provides the basis for most models of learning, memory and development in neural networks. The challenge for neuromorphic system designers is to find out efficient architectures to process accurately and speedily plasticity rules for a large number of synaptic connections. In this work, we propose a configurable architecture for real-time synaptic plasticity computation. Based on a dedicated plasticity processor, the architecture runs plasticity rules after a predefined configuration. As proof of concept, we implement on a commercial FPGA a biologically inspired form of spike timing-dependent plasticity (STDP) with complex time dependencies between pairs of pre- and post-synaptic spikes. Experimental results evaluate computation accuracy and speed as well as the number of synaptic connections we can process.
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on; 10/2008
