S.-T. Ryu

Korea Advanced Institute of Science and Technology, Sŏul, Seoul, South Korea

Are you S.-T. Ryu?

Claim your profile

Publications (4)1.86 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes [1]. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures [2-5] made contributions in realizing high-speed single-channel ADCs [2-4] with high resolution [5] by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with power taking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in [5], is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept.
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 03/2015; 58:470-471. DOI:10.1109/ISSCC.2015.7063130
  • [Show abstract] [Hide abstract]
    ABSTRACT: Recently reported high-speed ADCs have mostly taken advantage of time-interleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases, the power consumption of the front-end flash ADC becomes significant, which reduces the efficiency. In addition, if the target speed is higher than the frequency achievable by a single flash ADC, the FATI SAR ADC should be time-interleaved with multiple flash ADCs. The timing skew calibration scheme reported in [2] cannot be applied in this case. Considering these issues, this work introduces an advanced FATI SAR ADC with a folding-flash (F-flash) ADC that reduces the power burden placed upon a flash ADC. In addition, 2× time interleaving is applied in an effort to lower the conversion rate of the flash ADC (time-interleaved FATI SAR ADC). The offset and timing skew of each channel are calibrated in the background.
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 03/2015; 58:464-465. DOI:10.1109/ISSCC.2015.7063127
  • S.-H. Cho · H.-D. Lee · K.-D. Kim · S.-T. Ryu · J.-K. Kwon ·
    [Show abstract] [Hide abstract]
    ABSTRACT: A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of 107 and 109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc.
    Electronics Letters 04/2010; 46(5-46):335 - 337. DOI:10.1049/el.2010.3553 · 0.93 Impact Factor
  • S.-H. Cho · C.-K. Lee · B.R.S. Sung · S.-T. Ryu ·
    [Show abstract] [Hide abstract]
    ABSTRACT: A digital error correction technique with negligible hardware overhead is proposed for binary successive approximation ADCs. A redundant decision phase is inserted between the normal SAR operations, and the coarse decision error caused by incomplete DAC settling is corrected by a digital code addition. The relaxed DAC settling requirement for coarse decision increases the conversion speed.
    Electronics Letters 05/2009; 45(8-45):395 - 397. DOI:10.1049/el.2009.3738 · 0.93 Impact Factor