K. Hansen

Deutsches Elektronen-Synchrotron, Hamburg, Hamburg, Germany

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Publications (42)21.96 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A pixel-level 8-bit 5-MS/s Wilkinson-type analog-to-digital converter was designed and fabricated in the IBM 8M1P 130-nm CMOS technology. The pixel blocks are implemented with a core area of 130 μm by 140 μm, consuming about 560 μW at 1.2 V. Taking the measured dynamic range of 0.86 V into account, a signal-to-noise ratio above 65 dB was achieved for small signal amplitudes. The maximum differential and integral nonlinearity remains well below 0.4 LSB and 0.5 LSB, respectively. The conversion time is 160 ns, and the energy per conversion step 470 fJ. The digitizer permits the trimming of gain and offset.
    IEEE Transactions on Nuclear Science 01/2013; 60(5):3843-3851. · 1.22 Impact Factor
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    ABSTRACT: The DSSC (DEPFET Sensor with Signal Compression) consortium develops a IMPixel detector for low energy X-rays at the European XFEL. The XFEL will produce 10 bursts per second, each containing 2880 X-ray pulses with a repetition rate of 4.5 MHz. X-ray photons of 0.5 - 6 keV are absorbed in hexagonal DEPFET pixels of 229 × 204 μm2 pitch with a nonlinear characteristic to achieve a high dynamic range. The sensors will be bump bonded to readout ASICs of 64 × 64 pixels. Each pixel contains a filter with trapezoidal weighting function, a single slope ADC of 8-9 Bit resolution and a digital memory to store 640 events. A veto mechanism allows to discard uninteresting events. The digital hit data is read out serially during the ≈100 ms long burst gaps. Prototype matrix chips of 8 × 8 pixels with the full functionality have been produced and characterized electronically and with DEPFET sensors. The architecture and the design of the 8 × 8 ASIC, measured results and an outlook to the large 64 × 64 pixel chip will be presented.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
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    ABSTRACT: The DSSC (DEPFET Sensor with Signal Compression) is a new instrument with non-linear compression of the input signal in the sensor and with parallel signal processing (filtering, linear amplification, and digitization) for all pixels. The DSSC will serve as 2d imaging detector at the European X-ray Free Electron Laser (XFEL.EU) currently under construction in Hamburg, Germany. The DSSC design goal is to achieve at the same time single photon detection and high dynamic range of about 104 photons, both for photon energies down to 0.5 keY and read-out speeds up to 4.5 MHz. Realization of this goal requires an accurate calibration of the non-linear system response (NLSR) over the full dynamic range of the detector. We present our strategy for calibrating the NLSR, for each of the 1024 × 1024 DSSC pixels, in the laboratory. The feasibility of our calibration strategy is demonstrated experimentally by calibrating the NLSR of a DSSC prototype set-up consisting of a prototype DEPFET sensor with non-linear signal compression connected to a prototype read-out ASIC.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
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    ABSTRACT: The DSSC collaboration is developing an instrument to detect synchrotron X-rays (E > 0.5 keV) at the European XFEL. The DEPFET based sensors with integrated signal compression will be read out by 16 dedicated readout ASICs per sensor main board. Data are acquired during the XFEL burst (≈ 600 µs) at a rate of up to 4.5 MHz, and subsequently read out by the DAQ readout chain during the approximately 99.4 ms long burst gaps. The DAQ readout chain comprises two FPGA-based detector specific modules (I/O Board and Patch Panel Transceiver), which will be described in detail. A concentrator stage (Trainbuilder), which is common to all 2D detectors and part of the general XFEL DAQ, receives the data, and forwards them to the back-end storage facility. Each sensor main board has an I/O Board. Its purpose is to concentrate the data of the 16 low-speed channels of the ASICs into four high-speed serial links. The I/O Board also controls the shutdown of the analog sections during the readout phase to minimize the power consumption of the DSSC detector. The accumulated data will be sent to the Patch Panel Transceivers residing on the head of the detector. A Patch Panel Transceiver receives the XFEL front-end electronics (FEE) clock (≈ 99 MHz) and commands from the master Clock & Control unit. In addition, it provides the ASICs with control telegrams generated by the FPGA. An on-board PLL generates the ADC sampling clock of approximately 700 MHz, which is derived from, and in phase with the XFEL FEE clock.
    01/2011;
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    ABSTRACT: The DSSC (DEPFET Sensor with Signal Compression) is a new instrument with non-linear compression of the input signal in the sensor and with parallel signal processing (filtering, linear amplification, and digitization) for all pixels. The design goal is to achieve at the same time single photon detection and high dynamic range, both for photon energies down to 0.5 keV and read-out speeds up to 4.5 MHz. Realization of this goal requires an accurate calibration of the non-linear system gain (NLSG), i.e. of the non-linear dependence of the digital DSSC output signal on the input signal charge generated by incident photons, over the full dynamic range of the detector. We present an overview of our basic strategy for calibrating the NLSG. The feasibility of our calibration strategy is demonstrated using our system simulation package, which is briefly described. Finally, we demonstrate the DSSC capabilities by simulating the measurement of a T4 virus diffraction image as recorded at the Linac Coherent Light Source.
    01/2011;
  • Karsten Hansen, Helmut Klar, Dirk Muntefering
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    ABSTRACT: A description of the camera-head electronics of the DSSC mega-pixel X-ray imager is given. The integration of 32 sensor chips, 256 ASICs, 112 PCBs, and 16 flex cables in the space of 241mm × 251mm × 224mm underlines its compactness. Prototypes of subassemblies behind the readout-ASIC layer are designed and fabricated. Measurement results of the main functionalities clock distribution, power cycling, and clear-pulse generation are presented. A rms-timing jitter of 2.5 ps is achieved for the distribution of an 800-MHz ±290-mV clock signal. A settling time of 10 µs and a ripple in the millivolt range are achieved for 10-Hz cycling of the 1.2-V ASIC-power nets at a load current of 2.9 A. The feasibility of 600-µs long trains containing 60-ns FWHM pulses with 10-ns rise and fall times at a repetition rate of 4.5MHz is demonstrated. Low and high levels are adjustable between 2V and 22.5V for a 2.5-Ω∥3.6-nF load.
    01/2011;
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    ABSTRACT: A pixel-level 8-bit 5-MS/s digitizer for the DSSC X-ray imager utilizing the method of Wilkinson is presented. The timing information is generated column-wise by means of an 8-bit Gray-code counter. The 625-ps time stamps are distributed to the column pixels through 13-mm long shielded coplanar waveguides. Pixel-internal blocks comprise a sample-and-hold stage with current source for ramp generation, a temperature-compensated and supply voltage-stabilized reference circuitry, a comparator, a bank of eight receivers with latches for the time stamps, and control logic. These pixel-internal and global devices in 130-nm CMOS technology occupy 0.015 and 0.012 mm2, respectively. The power consumption amounts to at 1.2-V supply voltage. Taking the 0.8-V dynamic range into account, the simulated rms-noise voltage of about corresponds to a signal-to-noise ratio above 70 dB. The differential and integral nonlinearity is expected to remain below 0.4 LSB and 1 LSB, respectively. All results promise the compliance with underlying requirements.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2011; · 1.14 Impact Factor
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    ABSTRACT: A single-slope 8-bit 5-MS/s Wilkinson-type analog-to-digital converter for the DSSC mega-pixel X-ray imager was designed. Due to its simplicity, low power consumption, and small area requirement this type of ADC is suitable for pixel-level implementations. 625-ps time stamps are generated globally by means of an 8-bit Gray-code counter. They are distributed column-wise to the pixel blocks together with a conversion-start signal along 13-mm long transmission lines. The analog input voltage is sampled-and-held on a capacitor. A pixel-internal current source is used to generate a voltage ramp. The conversion into a digital word is done when the ramp voltage equals the reference voltage, and the corresponding time stamp is latched. The final readout chip will be a 64-by-64 pixel matrix. The chip prototype comprises an 8-by-8 ADC matrix representing a single 64-pixel column of the final matrix. It is fabricated in the IBM 8M1P 130-nm CMOS technology. Linearity, noise, and temperature- dependent effects are evaluated. Measurements demonstrate the achievement of a signal-to-noise ratio of 67 dB, a mean DNL of less than 0.3 LSB, and an INL below 0.5 LSB for the 5-MHz sampling rate. The area and power dissipation of the ADC's pixel circuitry amounts to 0.0139 mm2 and 634 µW, respectively. The global blocks require an area of 0.0143 mm2, and consume a mean power of 3.07 mW.
    01/2011;
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    ABSTRACT: The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E >; 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm<sup>2</sup> area, each one containing a low-noise (<; 50 e<sup>-</sup>) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of >; 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to <; 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.
    Nuclear Science Symposium Conference Record (NSS/MIC), 2010 IEEE; 12/2010
  • Source
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    ABSTRACT: The new DSSC (DEPFET sensor with signal compression) detector system is being developed in order to fulfil the requirements of the future XFEL in Hamburg. The instrument will be able to record X-ray images with a maximum frame rate of 5 MHz and to achieve a high dynamic range. The system is based on a silicon pixel sensor with a new designed non-linear-DEPFET as a central amplifier structure. The detector chip is bump-bonded to mixed signal readout ASICs that provide full parallel readout and temporary data storage. The signals coming from the detector are processed by an analog filter, immediately digitized by 8-ENOB ADCs and locally stored in a custom designed memory. The ASICs are designed in 130 nm CMOS technology. During the time gap of 99 ms of the XFEL machine, the digital data are sent off the focal plane to a DAQ electronics that acts as an interface to the back-end of the whole instrument. The pixel sensor has been designed so as to combine high energy resolution at low signal charge with high dynamic range. This has been motivated by the desire to be able to be sensitive to single low energy photons and, at the same time, to measure at other positions of the detector signals corresponding to up to 104 photons of 1 keV. In order to fit this dynamic range into a reasonable output signal swing, achieving at the same time single photon resolution, a strongly non-linear characteristic is required. The new proposed DEPFET provides the required dynamic range compression at the sensor level, considerably facilitating the task of the electronics. At the same time the DEPFET charge handling capacitance is enormously increased with respect to standard DEPFETs. The sensor matrix will comprise 1024×1024 pixels of hexagonal shape with a side-length of . The simultaneous implementation of the 5 MHz frame rate, of the single low-energy photon resolution and of the high dynamic range goes beyond all the existing instruments and requires the development of new concepts and technologies.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2010; · 1.14 Impact Factor
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    ABSTRACT: A system-level model of a low-noise high-speed mega-pixel camera with gain compression for X-ray photon correlation spectroscopy experiments at the European XFEL is presented. The model comprises the full signal chain from the sensor element via amplifier/filter and digitizer to the memory. The influence of gain- and offset errors as well as noise on the experiment-relevant image fidelity and intensity correlation function is discussed and compensation techniques are developed. A case study demonstrates the achievable efficiency of the chosen system parameters.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2010; · 1.14 Impact Factor
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    ABSTRACT: Fast counting applications with energy discrimination like X-ray absorption spectroscopy require an energy resolution of some hundred eV even at highest count rates and ask for small form factors. The development, fabrication and test of a small number of 7-cell Si-drift detectors have been successfully finished at DESY fitting these claims with a good cost-versus-performance tradeoff. The monolithic 7-cell sensor chip and a corresponding readout chip are the key components of the sensor head. The module's length and wrench size amounts to 21.2 and 1.6 cm, respectively. Its active area is ~ 7 times 7 mm<sup>2</sup> and main energy range is 2.5 to 18 keV. Between ~ 5 and 20 keV the nonlinearity in a six-modules setup is well within plusmn 2% and plusmn 0.5% when uncompensated and compensated, respectively. The Cu-K<sub>alpha</sub> line width is (271 plusmn 46) eV when operated at 10degC. With the best SDD chip we achieved (223 plusmn 7) eV at 10degC and (294 plusmn 10) eV at 24degC . By selection of the three best devices the spectral resolution reaches 400 and 600 eV at 10degC and a sum-count rate of 3.3middot10<sup>6</sup> s<sup>-1</sup> and 6.7middot10<sup>6</sup> s<sup>-1</sup>, respectively. XAFS measurements have shown that the peak shift and line-width variations remain below 5 eV and 17 eV, respectively.
    IEEE Transactions on Nuclear Science 07/2009; · 1.22 Impact Factor
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    ABSTRACT: In this paper results are presented from fluorescence-yield X-ray absorption fine-structure spectroscopy measurements with a new seven-cell silicon drift detector (SDD) module. The complete module, including an integrated circuit for the detector readout, was developed and realised at DESY utilizing a monolithic seven-cell SDD. The new detector module is optimized for applications like XAFS which require an energy resolution of approximately 250-300 eV (FWHM Mn Kalpha) at high count rates. Measurements during the commissioning phase proved the excellent performance for this type of application.
    Journal of Synchrotron Radiation 04/2009; 16(Pt 2):293-8. · 2.19 Impact Factor
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    ABSTRACT: We propose a new detector system capable to fulfil the requirements of the future XFEL in Hamburg. The instrument will be able to record X-ray images with a maximum frame rate of 5MHz and to achieve a high dynamic range. The system is based on a pixel-silicon sensor with a new designed non-linear-DEPFET as a central amplifier structure. The detector chip is bump-bonded to a set of mixed signal readout ASICs that provide full parallel readout. The signals coming from the detector, after having been processed by an analog filter, are immediately digitized by a series of 8-ENOB ADCs and locally stored in a custom designed memory also integrated in the ASICs designed in the 130nm CMOS technology. During the time gap of 99ms of the XFEL machine, the digital data are sent off the focal plane to a DAQ electronics that acts as an interface to the back-end of the whole instrument. The pixel sensor has been designed so as to combine high energy resolution at low signal charge with high dynamic range. This has been motivated by the desire to be able to be sensitive to single low energy photons and, at the same time, to measure at other positions of the detector signals corresponding to up to 10<sup>4</sup> photons of 1keV. In order to fit this dynamic range into a reasonable output signal swing, achieving at the same time single photon resolution, a strongly non linear characteristics is required. The new proposed DEPFET provides the required dynamic range compression at the sensor level, considerably facilitating the task of the electronics. At the same time the DEPFET charge handling capacitance is enormously increased with respect to standard DEPFETs. The Pixel matrix will have a format of 1024×1024 with a pixel size of 200×200 µm<sup>2</sup>.
    Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE; 11/2008
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    ABSTRACT: A new Si-drift detector module for fast X-ray spectroscopy experiments was developed and realized. The Peltier-cooled module comprises a sensor with 7×7-mm2 active area, an integrated circuit for amplification, shaping and detection, storage, and derandomized readout of signal pulses in parallel, and amplifiers for line driving. The compactness and hexagonal shape of the module with a wrench size of 16 mm allow very short distances to the specimen and multi-module arrangements. The power dissipation is 186 mW. At a shaper peaking time of 190 ns and an integration time of 450 ns an electronic rms noise of ∼11 electrons was achieved. When operated at , FWHM line widths around 260 and 460 eV (Cu-Kα) were obtained at low rates and at sum-count rates of 1.7 MHz, respectively. The peak shift is below 1% for a broad range of count rates. At 1.7-MHz sum-count rate the throughput loss amounts to 30%.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 05/2008; · 1.14 Impact Factor
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    ABSTRACT: Ten detector modules based on monolithic 7-cell Si-drift detectors with integrated junction field effect transistors (JFETs) are currently under production. The modules’ hexagonal shape with a wrench size of 16 mm allows very small distances to the samples and a compact multi-module arrangement. The sensors have active areas of and a thickness of . A proper spectroscopy operation of all modules was obtained by five common supply voltages and a 6th voltage which must be individually adopted. Detector capacitances varied from 83 to 145 fF, where statistical spreading caused by device mismatch amounts to 0.4%. On-chip scattering of the JFET's transconductance and source potential in a source-follower configuration are around 1%. Their spreading caused by process variations and device mismatch remain below 8%. Typical spectral resolution and non-linearity is about 300 eV and below 1% between 4.5 and 18 keV, respectively. After irradiation with a total dose of the resolution decreases by ∼40%. By shielding the cell borders and JFETs from direct irradiation with usage of a Zr mask, a spectral peak-to-valley ratio of ∼1000 was achieved.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2008; · 1.14 Impact Factor
  • I. Diehl, K. Hansen, C. Reckleben
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    ABSTRACT: This paper describes a mixed-signal seven-channel ASIC in 0.35-mum BiCMOS technology for the readout of Si-drift detectors used in X-ray spectroscopy. An integral count rate of more than four million pulses per second can be achieved. Count rate- and photon energy-related changes of the input pulse shape are compensated by a baseline-holding circuit, where the baseline instability remains below 1%. Within an input dynamic range between 1.9 mV and 7.2 mV a non-linearity below 1% can be reached. The equivalent input-noise voltage amounts to 31 muV<sub>rms</sub>. At maximum output voltage a channel-to-channel crosstalk of ~0.3% was measured. The power consumption of the readout chip is ~15 mW per channel. The functionalities of the main circuit blocks as well as experimental results are presented.
    Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European; 10/2007
  • Source
    Edmund Welter, Karsten Hansen
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    ABSTRACT: A novel 7 cell Silicon Drift Detector (SDD) module for X-Ray Absorption Fine Structure Spectroscopy (XAFS) and similar methods is developed at the Hamburger Synchrotron Strahlungslabor at Deutsches Elektronen Synchrotron. The monolithic 7 cell SDD detector chips were delivered by PN Sensors (Munich, Germany). Each cell has an active area of 7 mm2. In this paper we report results from the spatially resolved spectroscopic characterization of the SDD and their consequences for the final design of the complete detector modules. A specialized read out chip is currently developed at DESY and will make it possible to achieve a maximum count rate of 600 Kcps/detector cell.
    AIP Conference Proceedings. 02/2007; 882(1).
  • K. Hansen, C. Reckleben
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    ABSTRACT: We report on the temperature and count-rate dependent noise behavior of an Si-drift detector system using an on-sensor integrated JFET in a source-follower configuration. The readout chain of a 0.8-μm BiCMOS chip consists of a fully differential low-noise postamplifier, current-mode shaper with gated integrator, and analog storage cell. Six channels are processed in parallel using a 6 : 1 multiplexer buffered by a 100-Ω line driver. The readout chain's power dissipation is ∼15 mW/channel. The indexes for parallel, serial, and 1/f noise of the time-variant signal processor are calculated using weighting functions. For a detector capacitance of ∼140 fF and low count rates, the chip's and total electronics' input-referred equivalent noise charge is about 20 and 23 rms electrons, respectively. Due to an almost quadratical increase of the noise indexes with increasing count rate, the signal current deteriorates so that the spectral resolution of a Cu-K<sub>α</sub>-emission line at 20°C decreases from ∼300 eV (full-width at half-maximum) at low count rates to ∼850 eV at 600 kilocounts per second. The investigation of the temperature-dependent leakage current for different detectors leads to current densities between 1.5 pA/mm<sup>2</sup> and 3 pA/mm<sup>2</sup> at 20°C. The simulated and experimental data verify the theoretical results for a wide range of count rates and sensor temperatures.
    IEEE Transactions on Nuclear Science 01/2005; · 1.22 Impact Factor
  • K. Hansen, C. Reckleben
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    ABSTRACT: We report on the spectral peak-shift behavior of a Si-drift detector with integrated JFET operated in a source follower configuration. The experimental results are based on the measurements of the JFET's source voltage in the time domain and the analysis of the corresponding multiline X-ray fluorescence spectra. The transient measurements confirm a slew-rate limited decay of the source voltage pulses, which is attributed to the I-V characteristic of the JFET's gate-to-channel junction. We found that the slew rate depends linearly on the product of the center of energy and the count rate. Transient analysis of SDD/JFET circuit model and a new BiCMOS readout chip show a baseline shift, which is directly proportional to the slew rate and responsible for the peak shift. Considering the offset and gain of the subsequent spectroscopy system, the simulated peak positions agreed very closely with the results obtained from the measurements.
    IEEE Transactions on Nuclear Science 07/2004; · 1.22 Impact Factor

Publication Stats

87 Citations
21.96 Total Impact Points

Institutions

  • 1998–2013
    • Deutsches Elektronen-Synchrotron
      Hamburg, Hamburg, Germany
  • 2010
    • Universität Heidelberg
      • Institute for Computer Engineering
      Heidelberg, Baden-Wuerttemberg, Germany
  • 2000
    • University of Hamburg
      • Institut für Experimentalphysik
      Hamburg, Hamburg, Germany