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Publications (6)3.81 Total impact

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    ABSTRACT: Hot carrier degradation is critical for LDMOS transistors especially in applications where inductive loads are repetitively switched. In this work, a model for predicting the hot carrier degradation of an LDMOS in dynamic operation conditions is developed and verified for a device driving an inductive load in repetitive clamping mode. Device simulations are performed using the hydrodynamic model. Based on these simulations the physical mechanism of hot carrier degradation is investigated. The results are verified experimentally by photon-emission microscopy. Monte-Carlo simulation delivers profound insight into the spatial and energy distribution of the carriers impinging on the Si/SiO<sub>2</sub>-interface.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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    ABSTRACT: The drift of electrical parameters due to the injection of high energetic ¿hot¿ carriers into the oxide during operation is a serious concern regarding the reliability of lateral double-diffused transistors (LDMOSFETs). This is amplified by down-scaling, increasing the electric field in the drift region and thus the rate of hot carrier generation. As a consequence, profound knowledge of the hot carrier degradation is required for future device designs and the modeling of hot carrier degradation in various application modes. In this work, a comprehensive analysis of the hot carrier degradation at elevated drain voltage in an n-type LDMOSFET is presented. Photo-emission microscopy is used to detect the position of the impact ionization spot. The results are shown to be in good agreement with device simulation using the drift diffusion model and allow explaining the gate-voltage dependence of the degradation of R<sub>on</sub>. By Monte-Carlo simulation, the energy and spatial distribution of hot electrons and holes impinging on the oxide interface of an LDMOSFET is calculated.
    Integrated Reliability Workshop Final Report, 2009. IRW '09. IEEE International; 11/2009
  • H. Reisinger, A. Spitzer
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    ABSTRACT: The time‐dependent dielectric breakdown (TDDB) characteristics of thin oxide–nitride–oxide (ONO) films containing 4 nm of Si 3 N 4 were found to be exclusively determined by statistical thickness fluctuations of the Si 3 N 4 layer. A two‐parameter statistical model describes this roughness and explains experimental TDDB data. A simple growth model combined with the statistical model reduces the number of parameters to one. It is consistent with TDDB data and is in quantitative agreement with transmission electron microscopy and x‐ray photoelectron spectroscopy data and is able to explain the origin of the roughness. On an ONO with a 4 nm Si 3 N 4 layer and an area of 8 cm<sup>2</sup>—corresponding to the total storage area of a 256 Mbit dynamic random access memory—the thinnest point in the Si 3 N 4 can be expected to be below 10 Å. So eliminating the Si 3 N 4 roughness would bring a drastic improvement in reliability. © 1996 American Institute of Physics.
    Journal of Applied Physics 04/1996; · 2.21 Impact Factor
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    ABSTRACT: A capacitor based on an electrochemically etched macroporous silicon substrate and a layered dielectric (ONO) is presented. This solid-state technology allows us to realize values of specific capacitance which so far could only be reached by electrolytic capacitors. The dependence of the capacitance on temperature, frequency, applied bias and time of operation is found to be negligible. Due to a low series resistance and a operating temperature of at least 200 °C the device withstands high a.c. currents. Being a silicon chip, the capacitor is fully compatible with today's surface mounted device and multi-chip module technologies.
    Thin Solid Films 01/1996; 276(1):138-142. · 1.60 Impact Factor
  • A. Spitzer, H. Reisinger, W. Honlein
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    ABSTRACT: The impact of the thicknesses of the nitride- and oxide layers on the performance of a 5nm ONO-layer was investigated. For an optimized 5nm ONO-dielectric tbd 63% at 5MV/cm was found to be above 1012sec. In this dielectric the charge transport in the oxide layers is due to direct tunneling processes and the wear-out properties are dominated by the nitride layer. The limiting factors for the reduction of the individual layers of the stacked dielectric are discussed.
    01/1990;
  • H. Reisinger, A. Spitzer
    Journal of Pediatric Health Care - J PEDIATR HEALTH CARE. 01/1989;