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G. Van der Plas,
P. Limaye,
I. Loi,
A. Mercha,
H. Oprins,
C. Torregiani,
S. Thijs,
D. Linten,
M. Stucchi,
G. Katti, [......],
M. Dehan,
M. Nelis,
R. Agarwal,
A. Pullini,
F. Angiolini,
L. Benini,
W. Dehaene,
Y. Travaly,
E. Beyne,
P. Marchal
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ABSTRACT: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.
IEEE Journal of Solid-State Circuits 02/2011; · 3.23 Impact Factor
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ABSTRACT: Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to guarantee the required mechanical stability and rigidity to the thin wafer during subsequent backside processing. The temporary bonding approach followed by Imec is based on the adhesive material HT10.10 from Brewer Science (WaferBond<sup>®</sup> HT-10.10). The thermal and chemical stability of the temporary adhesive layer has been fully assessed and characterized in a 300mm production line, and for the first time we report on the full integration of thin wafer handling with backside processing on 300mm CMOS wafers.
3D Systems Integration Conference (3DIC), 2010 IEEE International; 12/2010
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ABSTRACT: In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafer scale by means of wafer bonding using classical metallization schemes found in IC's such as Al and Cu interconnect technologies. The wafer to wafer stacking is accomplished by back to face aligned wafer bonding using a combination of polymer bonding and copper to copper thermo-compression bonding. The Cu TSV-last process is inserted after the integration of a classical Al interconnect scheme. The top wafer is thinned down to 25μm and bonded to the landing wafer by hybrid Cu-Cu bonding in a high force bonding tool. Measurements of TSV interconnect chain structures covering the full wafer surface are provided as a demonstration of the relevance of such a process route.
Interconnect Technology Conference (IITC), 2010 International; 07/2010
