[Show abstract][Hide abstract] ABSTRACT: A variable delay line (VDL) is designed on a 130-nm CMOS process. Post-layout simulation results show that the VDL has a phase tuning range of 100 degrees at 60 GHz. It exhibits a wideband matching to 50-Ohm terminations from 20 GHz up to exceeding 80 GHz. The group delay variation is less than 4 ps within a bandwidth of 10 GHz. At its maximum phase shift, the VDL introduces a loss of 6 dB. The design features a small footprint of 430 mum times 220 mum and can be easily extended to provide wider phase tuning range.
Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on; 06/2008