[show abstract][hide abstract] ABSTRACT: A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um<sup>2</sup>) and low voltage (0.171 um<sup>2</sup>) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
[show abstract][hide abstract] ABSTRACT: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured f<sub>T</sub>/f<sub>MAX</sub> values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm L<sub>gate</sub> transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009