P. Maj

AGH University of Science and Technology in Kraków, Cracovia, Lesser Poland Voivodeship, Poland

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Publications (50)30.67 Total impact

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    ABSTRACT: The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80 μm) were also bonded to silicon pixelated sensors (with a pixel pitch of 100 μm) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39 e- and 70 e- , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52 μV/e- as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational.
    IEEE Transactions on Nuclear Science 02/2015; 62(1):349-358. DOI:10.1109/TNS.2014.2378784 · 1.46 Impact Factor
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    ABSTRACT: The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.
    IEEE Transactions on Nuclear Science 02/2015; 62(1):359-367. DOI:10.1109/TNS.2014.2385595 · 1.46 Impact Factor
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    ABSTRACT: Advances in semiconductor technologies, enable the design of hybrid pixel detectors with ever smaller pixel sizes while maintaining good performance of analogue circuits. Along with the decrease in the size of pixels new, previously unaddressed phenomena are beginning to play an important role. One such phenomenon is the charge sharing effect, where the charge generated by a particle in the vicinity of the pixel's border is collected by two or more different detector electrodes and processed in part by two or more independent pixels. In systems operating in the single photon counting (SPC) mode which compares the amplitude of the recorded signal with a predetermined threshold, this may reduce or increase the number of photons counted. In systems which measure the amplitude of the signal recorded, this phenomenon can lead to incorrect results of the amplitude measurements. In order to investigate the effect of charge sharing, measurements were conducted using silicon pixel detectors with the thickness of 300 μ m and 1 mm, 100 μ m × 100 μ m pixel size, connected to the PXD18k ASIC. The pixel array was scanned with 16 keV narrow pencil beam. The measurement setup and the results of the measurements are presented in the article.
    Journal of Instrumentation 02/2015; 10(02):C02006-C02006. DOI:10.1088/1748-0221/10/02/C02006 · 1.53 Impact Factor
  • P Maj
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    ABSTRACT: An important trend in the design of readout electronics working in the single photon counting mode for hybrid pixel detectors is to minimize the single pixel area without sacrificing its functionality. This is the reason why many digital and analog blocks are made with the smallest, or next to smallest, transistors possible. This causes a problem with matching among the whole pixel matrix which is acceptable by designers and, of course, it should be corrected with the use of dedicated circuitry, which, by the same rule of minimizing devices, suffers from the mismatch. Therefore, the output of such a correction circuit, controlled by an ultra-small area DAC, is not only a non-linear function, but it is also often non-monotonic. As long as it can be used for proper correction of the DC operation points inside each pixel, it is acceptable, but the time required for correction plays an important role for both chip verification and the design of a big, multi-chip system. Therefore, we present two algorithms: a precise one and a fast one. The first algorithm is based on the noise hits profiles obtained during so called threshold scan procedures. The fast correction procedure is based on the trim DACs scan and it takes less than a minute in a SPC detector systems consisting of several thousands of pixels.
    Journal of Instrumentation 07/2014; 9(07):C07009. DOI:10.1088/1748-0221/9/07/C07009 · 1.53 Impact Factor
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    ABSTRACT: For many years hybrid pixel detectors working in the single photon counting mode have been used not only in high energy physics experiments but also for X-ray imaging applications. In these detectors each pixel has its independent electronic readout channel for photon by photon signal processing, what provides better image quality and possibility of counting photons only within a given energy window. There are different trends in development of hybrid pixel detectors. One is to use nanometer or 3D technologies to include more complex functionality in single pixel cell together with good parameters of analog front-end electronics and high maximum pulse throughput per single channel. Another trend is targeted at building large area X-ray cameras which can be used by industry or novel scientific experiments mainly in material science, physics and biology. In both trends the problems to be solved are similar, however the priorities are a little bit different. This paper presents the main issues related to the development of semiconductor pixel detector systems on the examples of produced integrated circuits.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
  • Piotr Maj
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    ABSTRACT: Hybrid pixel detectors working in single photon counting mode are very attractive solution for new experiments as their functionality increases and the single pixel size is getting smaller. This is possible due to new deep sub-micron technologies, which allows making smaller devices. However, making smaller devices has drawbacks, one of which is that matching of smaller transistors decreases, resulting in higher offset spread of DC operating points in channels. Having large area pixel detector containing over 20.000 channels an efficient correction circuit is required in each channel allowing effective trimming of the entire matrix including small percentage of exceptional pixels. If the readout circuit contains a discriminator, different correction circuits are used for minimization of the mismatch effect usually at the discriminator input. As the pixel size is minimized correction DACs quality is often degraded and therefore it is not only non-linear but also likely non-monotonic. The large multi-thousand channel systems requires fast calculation of the correction DACs values in order to make the whole system useful. The correction scheme implemented in the large area hybrid pixel detector readout circuit containing 23552 pixels with a size of 100um x 100um each will be presented together with adequate measurements and applied correction algorithms.
    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); 04/2014
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    ABSTRACT: A hybrid pixel detector operating in a single photon counting mode requires a pixel readout chip with the geometry that matches the geometry of the detector array. Stringent and growing requirements on smaller pixel size, higher data throughput and more sophisticated functionality are imposed for such imaging systems. CMOS nanometer or 3D technologies seem to be very attractive for pixel readout integrated circuits, especially in the case of implementing more complex functionality or advanced algorithms on the chip. However, these technologies are mainly driven by high density and very fast digital circuits, nevertheless in case of hybrid pixel detectors the analog performance of front-end electronics, such as noise, offset spreads or crosstalk minimization, are of primary importance. We will present some examples of our realization of these kind of ICs both in advance technologies (like 3D or 40 nm CMOS), as well as for commercial application where final yield is of primary importance.
    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); 04/2014
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    ABSTRACT: An important development in digital X-ray imaging systems is a pulse amplitude measurement in each pixel in real-time. A single readout pixel usually has the dimensions of 100 µm × 100 µm or lower, and as it has to accommodate the analog front-end amplifier and digital back-end readout logic, the area available for an ADC is extremely low. Thus, in the design of the ADC the most emphasis has to be put on decreasing its silicon area. Also, as a single readout chip consists of thousands of pixels, the allowed power budget per pixel is in the order of tens of microwatts, hence the power consumption of the converter has to be kept very low as well. This paper describes a design and measurement results of two 4-bit flash ADC prototypes, fabricated in 180 nm and 40 nm processes, which fit into a single pixel and can be used in future X-ray imaging systems. To make the comparison more meaningful, both designs share exactly the same architecture, have identical resolution and sample rate. The architecture of the design, layout comparison and obtained test results are presented.
    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); 04/2014
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    ABSTRACT: The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.
    IEEE Transactions on Nuclear Science 01/2014; 61(1). DOI:10.1109/TNS.2013.2294673 · 1.46 Impact Factor
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    ABSTRACT: Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.
    Proceedings of SPIE - The International Society for Optical Engineering 07/2013; DOI:10.1117/12.2031432 · 0.20 Impact Factor
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    Nuclear Physics A 05/2013; 904-905:1059. DOI:10.1016/j.nuclphysa.2013.02.193 · 2.50 Impact Factor
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    ABSTRACT: We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm×20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96×192 pixels with 100 μm×100 μm pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 μW/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 μV/e− and the equivalent noise charge is 168 e− rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2013; 697:32–39. DOI:10.1016/j.nima.2012.08.103 · 1.32 Impact Factor
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    ABSTRACT: This article describes the advantages of using the Field Programmable Gate Arrays (FPGA) for significant acceleration of Monte Carlo simulations leading to the fast verification of new ideas. An example of a real and challenging problem in the design of application specific integrated circuits (ASIC) for 2D X-ray imaging applications, namely the charge sharing effect in a highly segmented position sensor, is presented together with a detailed description of its software and hardware simulations. The implementation of the C8P1 algorithm is described at the hardware simulation level, including mathematical modeling parameters and tools used. As a result of the presented approach, simulations over 1000 times faster (compared to standard processor driven) are possible, reducing multi-dimensional simulation duration from days to minutes. The presented solution has helped identify and improve weak points in numerous versions of the C8P1 algorithm to mitigate the charge sharing effect and to implement an ASIC in ultra-deep sub-micron solution technology, which aims to improve medical, scientific and industrial X-ray imaging in terms of spectral and position sensitive measurements.
    Computer Modelling and Simulation (UKSim), 2013 UKSim 15th International Conference on; 01/2013
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    ABSTRACT: Charge sharing is the main limitation of pixel detectors used in spectroscopic applications, noting that this applies to both time and amplitude/energy spectroscopy. Even though, charge sharing was the subject of many studies, there is still no ultimate solution which could be implemented in the hardware to suppress the negative effects of charge sharing. This is mainly because of strong demand on low power dissipation and small silicon area of a single pixel. The first solution of this problem was proposed by CERN and consequently it was implemented in the Medipix III chip. However, due to pixel-to-pixel threshold dispersions and some imperfections of the simplified algorithm, the hit allocation was not functioning properly. We are presenting novel algorithms which allow proper hit allocation even at the presence of charge sharing. They can be implemented in an integrated circuit using a deep submicron technology. In performed simulations, we assumed not only diffusive charge spread occurring in the course of charge drifting towards the electrodes but also limitations in the readout electronics, i.e. signal fluctuations due to noise and mismatch (gain and offsets). The simulations show that using, for example, a silicon pixel detector in the low X-ray energy range, we have been able to perform proper hit position identification and use the information from summing inter-pixel nodes for spectroscopy measurements.
    Journal of Instrumentation 11/2012; 7(12). DOI:10.1088/1748-0221/7/12/C12020 · 1.53 Impact Factor
  • R. Szczygiel · P. Grybos · P. Maj
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    ABSTRACT: We report on high count rate and high frame rate measurements of a prototype IC named FPDR90, designed for readouts of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 is constructed in 90 nm CMOS technology and has dimensions of 4 mm×4 mm. Its main part is a matrix of 40×32 pixels with 100 μm×100 μm pixel size. The chip works in the single photon counting mode with two discriminators and two 16-bit ripple counters per pixel. The count rate per pixel depends on the effective CSA feedback resistance and can be set up to 6 Mcps. The FPDR90 can operate in the continuous readout mode, with zero dead time. Due to the architecture of digital blocks in pixel, one can select the number of bits read out from each counter from 1 to 16. Because in the FPDR90 prototype only one data output is available, the frame rate is 9 kfps and 72 kfps for 16 bits and 1 bit readout, respectively (with nominal clock frequency of 200 MHz).
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 07/2012; 680:56–60. DOI:10.1016/j.nima.2012.03.045 · 1.32 Impact Factor
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    ABSTRACT: Hybrid pixel detectors are becoming a standard in modern fast X-ray imaging for material science, physics and medicine. However, charge sharing effect is the main limitation in increasing position resolution of these systems and also for using them for spectroscopy applications. In this paper we present novel algorithms which allow proper hit allocation even in the case of charge sharing and which can easily be implemented in an integrated circuit using submicron technology. In our simulation we take into account both the spread of the charge in the detector as well as the expected noise and mismatch in the readout electronics. The simulation was performed for the pixel size 80 μm × 80 μm, for the input referred noise ranged from 75 e- rms to 150 e- rms and the charge deposited in the detector from 1100 e- to 6600 e-, which are typical values for soft X-rays.
    Industrial Technology (ICIT), 2012 IEEE International Conference on; 01/2012
  • P. Maj · A. Goral · P. Grybos
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    ABSTRACT: We present the DEDIXtest system, which is a tool for testing DEDIX chip - a 64-channel application specific integrated circuit (ASIC) designed for readout of silicon strip detectors used in X-ray imaging applications. For communication with ASIC we use the commercially available interface board featuring a real-time processor and a set of digital inputs and outputs controlled by a field programmable gate array. This application features a user interface module, which allows convenient definition of tasks for the program and clear presentation of measurement results. For validation of the developed software we performed a set of simple tests for each of the implemented procedures, using X-ray tubes applied in diffractometers.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
  • R. Szczygiel · P. Grybos · P. Maj
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    ABSTRACT: We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 μm × 100 μm pixel size. A 50 μm diameter circular passivation opening in each pixel allows connecting FPDR90 to a semiconductor detector using bump bonding technique. Each pixel contains a charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. To minimize the effective threshold spread at the discriminators inputs, one 7-bit and one 6-bit trim DACs are used in each pixel for threshold low and threshold high respectively. The data are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a nominal power consumption of 42 μW for nominal bias condition. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 μV/e- or 64 μV/e- in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e- rms and rises to 106 e- rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to 12 e- rms at the input. The maximum count rate per pixel depends on the effective CSA feedback resistance. A dead time in the front-end can be set as low as 117 ns (paralyzable model). The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure. Continuous readout is possible when only one threshold is used.
    IEEE Transactions on Nuclear Science 07/2011; 58(3-58):1361 - 1369. DOI:10.1109/TNS.2011.2142322 · 1.46 Impact Factor
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    ABSTRACT: Existence of the natural diffusive spread of charge carriers on the course of their drift towards collecting electrodes in planar, segmented detectors results in a division of the original cloud of carriers between neighboring channels. This paper presents the analysis of algorithms, implementable with reasonable circuit resources, whose task is to prevent degradation of the detective quantum efficiency in highly granular, digital pixel detectors. The immediate motivation of the work is a photon science application requesting simultaneous timing spectroscopy and 2D position sensitivity. Leading edge discrimination, provided it can be freed from uncertainties associated with the charge sharing, is used for timing the events. Analyzed solutions can naturally be extended to the amplitude spectroscopy with pixel detectors
    01/2011; DOI:10.1109/NSSMIC.2011.6153986