P. Maj

AGH University of Science and Technology in Kraków, Cracovia, Lesser Poland Voivodeship, Poland

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Publications (39)20.19 Total impact

  • P Maj
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    ABSTRACT: An important trend in the design of readout electronics working in the single photon counting mode for hybrid pixel detectors is to minimize the single pixel area without sacrificing its functionality. This is the reason why many digital and analog blocks are made with the smallest, or next to smallest, transistors possible. This causes a problem with matching among the whole pixel matrix which is acceptable by designers and, of course, it should be corrected with the use of dedicated circuitry, which, by the same rule of minimizing devices, suffers from the mismatch. Therefore, the output of such a correction circuit, controlled by an ultra-small area DAC, is not only a non-linear function, but it is also often non-monotonic. As long as it can be used for proper correction of the DC operation points inside each pixel, it is acceptable, but the time required for correction plays an important role for both chip verification and the design of a big, multi-chip system. Therefore, we present two algorithms: a precise one and a fast one. The first algorithm is based on the noise hits profiles obtained during so called threshold scan procedures. The fast correction procedure is based on the trim DACs scan and it takes less than a minute in a SPC detector systems consisting of several thousands of pixels.
    Journal of Instrumentation 07/2014; 9(07):C07009. · 1.66 Impact Factor
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    ABSTRACT: The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.
    IEEE Transactions on Nuclear Science 01/2014; 61(1). · 1.22 Impact Factor
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    ABSTRACT: Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.
    Proc SPIE 07/2013;
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    ABSTRACT: We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm×20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96×192 pixels with 100 μm×100 μm pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 μW/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 μV/e− and the equivalent noise charge is 168 e− rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2013; 697:32–39. · 1.14 Impact Factor
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    ABSTRACT: This article describes the advantages of using the Field Programmable Gate Arrays (FPGA) for significant acceleration of Monte Carlo simulations leading to the fast verification of new ideas. An example of a real and challenging problem in the design of application specific integrated circuits (ASIC) for 2D X-ray imaging applications, namely the charge sharing effect in a highly segmented position sensor, is presented together with a detailed description of its software and hardware simulations. The implementation of the C8P1 algorithm is described at the hardware simulation level, including mathematical modeling parameters and tools used. As a result of the presented approach, simulations over 1000 times faster (compared to standard processor driven) are possible, reducing multi-dimensional simulation duration from days to minutes. The presented solution has helped identify and improve weak points in numerous versions of the C8P1 algorithm to mitigate the charge sharing effect and to implement an ASIC in ultra-deep sub-micron solution technology, which aims to improve medical, scientific and industrial X-ray imaging in terms of spectral and position sensitive measurements.
    Computer Modelling and Simulation (UKSim), 2013 UKSim 15th International Conference on; 01/2013
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    Nuclear Physics A 01/2013; 904-905:1059. · 2.50 Impact Factor
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    ABSTRACT: Charge sharing is the main limitation of pixel detectors used in spectroscopic applications, noting that this applies to both time and amplitude/energy spectroscopy. Even though, charge sharing was the subject of many studies, there is still no ultimate solution which could be implemented in the hardware to suppress the negative effects of charge sharing. This is mainly because of strong demand on low power dissipation and small silicon area of a single pixel. The first solution of this problem was proposed by CERN and consequently it was implemented in the Medipix III chip. However, due to pixel-to-pixel threshold dispersions and some imperfections of the simplified algorithm, the hit allocation was not functioning properly. We are presenting novel algorithms which allow proper hit allocation even at the presence of charge sharing. They can be implemented in an integrated circuit using a deep submicron technology. In performed simulations, we assumed not only diffusive charge spread occurring in the course of charge drifting towards the electrodes but also limitations in the readout electronics, i.e. signal fluctuations due to noise and mismatch (gain and offsets). The simulations show that using, for example, a silicon pixel detector in the low X-ray energy range, we have been able to perform proper hit position identification and use the information from summing inter-pixel nodes for spectroscopy measurements.
    Journal of Instrumentation 11/2012; 7(12). · 1.66 Impact Factor
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    ABSTRACT: We report on high count rate and high frame rate measurements of a prototype IC named FPDR90, designed for readouts of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 is constructed in 90 nm CMOS technology and has dimensions of 4 mm×4 mm. Its main part is a matrix of 40×32 pixels with 100 μm×100 μm pixel size. The chip works in the single photon counting mode with two discriminators and two 16-bit ripple counters per pixel. The count rate per pixel depends on the effective CSA feedback resistance and can be set up to 6 Mcps. The FPDR90 can operate in the continuous readout mode, with zero dead time. Due to the architecture of digital blocks in pixel, one can select the number of bits read out from each counter from 1 to 16. Because in the FPDR90 prototype only one data output is available, the frame rate is 9 kfps and 72 kfps for 16 bits and 1 bit readout, respectively (with nominal clock frequency of 200 MHz).
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 07/2012; 680:56–60. · 1.14 Impact Factor
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    ABSTRACT: Hybrid pixel detectors are becoming a standard in modern fast X-ray imaging for material science, physics and medicine. However, charge sharing effect is the main limitation in increasing position resolution of these systems and also for using them for spectroscopy applications. In this paper we present novel algorithms which allow proper hit allocation even in the case of charge sharing and which can easily be implemented in an integrated circuit using submicron technology. In our simulation we take into account both the spread of the charge in the detector as well as the expected noise and mismatch in the readout electronics. The simulation was performed for the pixel size 80 μm × 80 μm, for the input referred noise ranged from 75 e- rms to 150 e- rms and the charge deposited in the detector from 1100 e- to 6600 e-, which are typical values for soft X-rays.
    Industrial Technology (ICIT), 2012 IEEE International Conference on; 01/2012
  • P. Maj, A. Goral, P. Grybos
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    ABSTRACT: We present the DEDIXtest system, which is a tool for testing DEDIX chip - a 64-channel application specific integrated circuit (ASIC) designed for readout of silicon strip detectors used in X-ray imaging applications. For communication with ASIC we use the commercially available interface board featuring a real-time processor and a set of digital inputs and outputs controlled by a field programmable gate array. This application features a user interface module, which allows convenient definition of tasks for the program and clear presentation of measurement results. For validation of the developed software we performed a set of simple tests for each of the implemented procedures, using X-ray tubes applied in diffractometers.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
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    ABSTRACT: We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 μm × 100 μm pixel size. A 50 μm diameter circular passivation opening in each pixel allows connecting FPDR90 to a semiconductor detector using bump bonding technique. Each pixel contains a charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. To minimize the effective threshold spread at the discriminators inputs, one 7-bit and one 6-bit trim DACs are used in each pixel for threshold low and threshold high respectively. The data are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a nominal power consumption of 42 μW for nominal bias condition. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 μV/e- or 64 μV/e- in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e- rms and rises to 106 e- rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to 12 e- rms at the input. The maximum count rate per pixel depends on the effective CSA feedback resistance. A dead time in the front-end can be set as low as 117 ns (paralyzable model). The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure. Continuous readout is possible when only one threshold is used.
    IEEE Transactions on Nuclear Science 07/2011; · 1.22 Impact Factor
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    ABSTRACT: This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 x 32 pixels with the size of 100µm x 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16- bit ripple counters. The nominal power consumption per pixel is 42 W. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 V/e  or 64 V/e  in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e  rms and rises to 106 e  rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e  rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.
    20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
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    ABSTRACT: Existence of the natural diffusive spread of charge carriers on the course of their drift towards collecting electrodes in planar, segmented detectors results in a division of the original cloud of carriers between neighboring channels. This paper presents the analysis of algorithms, implementable with reasonable circuit resources, whose task is to prevent degradation of the detective quantum efficiency in highly granular, digital pixel detectors. The immediate motivation of the work is a photon science application requesting simultaneous timing spectroscopy and 2D position sensitivity. Leading edge discrimination, provided it can be freed from uncertainties associated with the charge sharing, is used for timing the events. Analyzed solutions can naturally be extended to the amplitude spectroscopy with pixel detectors
    01/2011;
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    ABSTRACT: We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40×32 pixels with 100 μm ×100 μm pixel size. Each pixel contains a fast charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. The data from pixel matrix are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a static power consumption of 42 μW for nominal bias condition. The effective pulse shaping for nominal bias condition is 28 ns and the equivalent noise charge is only 106 e- rms (when the CSA connected to silicon pixel detector). In a high gain mode an average gain of the front-end electronics is 64 μV/e-. The effective offset spread (at the one sigma level) from pixel to pixel and with enabled trim DAC is only 0.76 mV (calculated to the CSA input it is only 12 e- rms). The maximum count rate per pixel depends on the effective CSA feedback resistance and the dead time in the front-end as low as 117 ns (paralyzable model) can be set. The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure or in the continuous readout mode with both a single threshold.
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: We report on the high count rate and high frame rate measurements of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 is designed in 90 nm CMOS technology and has dimensions of 4 mm × 4 mm. It's main part is a matrix of 40×32 pixels with 100 µm × 100 µm pixel size. The chip work in single photon counting mode with two discriminators and two 16-bit ripple counters per pixel. The count rate per pixel depends on the effective CSA feedback resistance and can be set up to 6 Mcps per pixel. The FPDR90 can operate in continuous readout mode, with a zero dead time. Due to the architecture of digital blocks in pixel, one can select the number of readout bits from each counter from 1 to 16 bits. Because in the FPDR90 prototype only one data output is available, the frame rate is 9 kHz and 72 kHz for 16 bits and 1 bit readout from single pixel respectively (with nominal clock frequency of 200 MHz).
    01/2011;
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    ABSTRACT: We report on the design of an integrated circuit called PXD18k dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The PXD18k has dimensions of 9.64 mm × 20 mm and is designed in CMOS 180 nm technology. The core of the IC is a matrix of 96×192 pixels with 100 µm ×100 µm pixel size working in a single photon counting mode. Each pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent threshold A and B) and two 16-bit ripple counters. To minimize the effective threshold spread, one 7-bit and one 5-bit trim DACs are used in each pixel for correction of threshold A and threshold B respectively. The data are read out via 8 LVDS outputs with 100 Mbps rate. The power consumption is dominated by the analog blocks and it is about 23 µW/pixel. The effective peaking time at the discriminator input is 30 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 42.5 µV/e− and an Equivalent Noise Charge with bump-bonded detector is 168 e− rms. The effective threshold spread at the discriminator input is only 1.79 mV (at one sigma level, with 7-bit trim DACs enabled). The count rate per pixel depends on the effective CSA feedback resistance and for a standard setting a dead time of the front-end electronics is 172 ns (paralyzable model). The PXD18k IC works with two energy thresholds in the readout mode separate from exposure. When operating with two different energy thresholds, acquisition and readout are interleaved and the readout dead time is 740 µs. The PXD18k can also operate in a continuous readout mode with zero dead time and one can select the number of bits readout from each pixel to optimize the IC frame rate. For example for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises up to 7.1 kHz.
    01/2011;
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    ABSTRACT: We have designed, fabricated in 90 nm technology and tested a prototype ASIC for readout of semiconductor pixel detectors for X-ray imaging applications. The 4mm × 4mm readout IC is working in single photon counting mode and contains a pixel matrix of 1280 readout channels with dimensions of 100um × 100um each. We present the architecture, the measurement results of this IC and our conclusions. To make this chip more attractive for novel experiments, we need to further increase single pixel functionality and at the same time reduce the pixel area. This leads us to the 3D technology with at least two layers: analogue and digital and additionally the sensor layer. We present the concept of the 3D hybrid pixel chip design with small pixel size and the ability to build a dead-space free large area pixel matrix.
    01/2011;
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    ABSTRACT: We report on the design of the VIPIC IC (Vertically Integrated Pixel Imaging Chip) designed for X-ray Photon Correlation Spectroscopy (XPCS) experiments by FNAL in collaboration with AGH-UST. The VIPIC chip is a prototype matrix with 64 × 64 pixels with 80 μm × 80 μm pixel size and consists of two layers: analog and digital. The single analog pixel cell consists of a charge sensitive amplifier, a shaper, a single current discriminator and trim DACs. The simulated gain is 52 μV/e<sup>-</sup>, the noise ENC <; 150 e<sup>-</sup> rms (with C<sub>det</sub>= 100 fF) and the peaking time t<sub>p</sub> <; 250 ns. The power consumption is 25 μW/pixel in the analog part. The digital layer of the VIPIC integrated circuit is divided into 16 readout groups of pixels read out in parallel via separate serial ports with nominal frequency of the 100 MHz clock using the LVDS standard. The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixels only) allows a dead-time free readout.
    Nuclear Science Symposium Conference Record (NSS/MIC), 2010 IEEE; 12/2010
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    ABSTRACT: We report on the design of a prototype IC called PX90 dedicated for readout of hybrid semiconductor detectors used for X-ray imaging applications. The PX90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40 × 32 pixels with 100 m × 100 m pixel size. A 60 m × 60 m square passivation opening in each pixel allows connecting PX90 to a semiconductor detector using stud bump bonding technique. Each pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two second stage amplifiers, two discriminators and two 16-bit ripple counters. The stages are DC-coupled and the front-end electronics uses a fully differential readout scheme. To minimize the effective threshold spread at the discriminators inputs, one 8-bit and one 7-bit trim DACs are used. The PX90 can operate in continuous readout mode and in readout mode separate from exposure. The readout of each pixel has some additional functionality, like compression mode or readout of only given number of bits from each pixel. The data are read out via a single LVDS output with 200 Mbps rate.
    IEEE Transactions on Nuclear Science 07/2010; · 1.22 Impact Factor