N. Nedovic,
A. Kristensson,
S. Parikh,
S. Reddy,
S. McLeod,
N. Tzartzanis,
K. Kanda, T. Yamamoto,
S. Matsubara,
M. Kibune, [......],
T. Yamabana,
T. Shibasaki,
Y. Tomita,
T. Hamada,
M. Sugawara,
T. Ikeuchi,
N. Kuwata,
H. Tamura,
J. Ogawa,
W. Walker
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ABSTRACT: A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.
IEEE Journal of Solid-State Circuits 11/2010; · 3.23 Impact Factor
