H. Konoura

Publications (2)0 Total impact

• Source

  Available from: ac.jp

  Conference Proceeding: Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures

  H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
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  ABSTRACT: Fault avoidance methods on dynamically reconfigurable devices have been proposed to extend device life-time, while their quantitative comparison has not been sufficiently presented. This paper shows results of quantitative life-time evaluation by simulating fault avoidance procedures of representative five methods under the same conditions of wear-out scenario, application and device architecture. Experimental results reveal 1) MTTF is highly correlated with the number of avoided faults, 2) there is the efficiency difference of spare usage in five fault avoidance methods, and 3) spares should be prevented from wear-out not to spoil life-time enhancement.
  Field Programmable Logic and Applications (FPL), 2011 International Conference on; 10/2011
• Source

  Available from: ac.jp

  Conference Proceeding: Coarse-grained dynamically reconfigurable architecture with flexible reliability

  D. Alnajiar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
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  ABSTRACT: This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.
  Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on; 10/2009