M.C.M. Soer

Universiteit Twente, Enschede, Overijssel, Netherlands

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Publications (10)10.61 Total impact

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    ABSTRACT: A spectrum analyzer requires a high linearity to handle strong signals, and at the same time a low NF to enable detection of much weaker signals. This is not only important for lab equipment, but also for the spectrum sensing part of cognitive radio, where low cost and integration is at a premium. Often there is a trade-off between linearity and noise: improving one degrades the other. Crosscorrelation can break this tradeoff by reducing noise at the expense of measurement time. An existing RF frontend in CMOS-technology with IIP3=+11dBm and NF=5.5 dB is duplicated and attenuators are put in front to increase linearity to IIP3=+24 dBm. The attenuation degrades NF, but by using crosscorrelation of the outputs of the two frontends, the effective NF is reduced to around 5 dB. In total, this results in a spurious-free dynamic range of 88 dB in 1MHz resolution bandwidth.
    IEEE Trans. on Circuits and Systems. 01/2012; 59-I:479-492.
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    ABSTRACT: Phased-Arrays are increasingly used, and require Silicon implementations to result in affordable multi-beam systems. In this paper, CMOS implementations of two novel analogue beamforming multi-channel receivers will be presented. A narrow-band highly linear system exploiting switches and capacitors in advanced CMOS is presented, implementing a fully passive switched capacitor vector modulator exploiting a zero-IF I/Q mixer: This technique is not applicable to very wideband phased-array receivers. These systems require true-time delay beamforming, which is implemented in the second CMOS implementation. An innovative gm-RC implementation of a true-time delay cell is exploited in a four-channel beamforming receiver with more than 1.5 GHz bandwidth, in a standard 0.13 um CMOS process. Professional phased-arrays can often not live with the dynamic range limitations imposed by these implementations. To that end a SiGe implementation of an integrated receiver was realized targeting a digital beamforming phased-array. Dynamic range and flexibility of use were the main driving factors. Alltogether, these results show large progress with respect to the feasibility of Silicon-based phased-array front-end implementation for commercial as well as professional phased-arrays.
    Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International; 01/2012
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    ABSTRACT: Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 01/2012;
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    ABSTRACT: A spectrum analyzer requires a high linearity to handle strong signals, and at the same time a low NF to enable detection of much weaker signals. This is not only important for lab equipment, but also for the spectrum sensing part of cognitive radio, where low cost and integration is at a premium. Often there is a trade-off between linearity and noise: improving one degrades the other. Crosscorrelation can break this trade-off by reducing noise at the expense of measurement time. An existing RF frontend in CMOS-technology with IIP3 = +11 dBm and NF = 5.5 dB is duplicated and attenuators are put in front to increase linearity to IIP3 = +24 dBm. The attenuation degrades NF, but by using crosscorrelation of the outputs of the two frontends, the effective NF is reduced to around 5 dB. In total, this results in a spurious-free dynamic range of 88 dB in 1 MHz resolution bandwidth.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2012; 59(3):479-492. · 2.24 Impact Factor
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    ABSTRACT: A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P<sub>1dB</sub>=2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).
    IEEE Journal of Solid-State Circuits 06/2011; · 3.06 Impact Factor
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    ABSTRACT: Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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    ABSTRACT: A 1-4-GHz 4-element phased array receiver front-end demonstrates spatial interferer rejection using null steering. Element phase and amplitude control are performed by a switched-capacitor vector modulator with integrated downconversion, utilizing a rational sine/cosine approximation. The 65-nm CMOS receiver achieves more than 20 dB of spatial interferer rejection up to an angular separation of 15°.
    IEEE Journal of Solid-State Circuits 01/2011; 46(12):2933-2942. · 3.06 Impact Factor
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    ABSTRACT: A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2010; · 2.24 Impact Factor
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    ABSTRACT: Spectrum sensing for cognitive radio requires a high linearity to handle strong signals, and at the same time a low noise figure (NF) to enable detection of much weaker signals. Often there is a trade-off between linearity and noise: improving one of them degrades the other. Cross-correlation can break this trade-off by reducing noise at the cost of measurement time. An existing RF front-end in CMOS-technology with IIP3=+11dBm and NF<6.5dB is duplicated and attenuators are put in front to increase linearity (IIP3=+24dBm). The attenuation degrades NF, but by using cross-correlation of the outputs of the two frontends, the NF is reduced to below 4dB. In total this results in a spurious-free dynamic range (SFDR) of 89dB in 1MHz resolution bandwidth (RBW).
    New Frontiers in Dynamic Spectrum, 2010 IEEE Symposium on; 05/2010
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    ABSTRACT: Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core for low conversion loss and low noise folding it is shown that it is possible to realize IIP3>11 dBm and NF<6.5dB, i.e. a remarkably high SFDR>79dB in 1MHz bandwidth over a decade of RF frequencies.
    Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009