-
[show abstract]
[hide abstract]
ABSTRACT: A systematic study on silicon native oxides grown in ambient air at room temperature is carried out
using ballistic electron emission microscopy. The electronic barrier height of Au/native oxide was
directly measured for native oxides at different oxidation stages. While the ballistic electron
transmission decreases with increasing oxidation time, the electronic barrier height remains the
same, even after oxidation for 1 week. After oxidation for 26 months, the oxide layer showed the
bulk-like SiO2 barrier; however, some local areas still show the same barrier height as that of an
Au/n-Si device. This demonstrates the non-uniformity of native oxide growth.
Journal of Applied Physics 03/2012; 111(4):054111. · 2.17 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We report upon a comprehensive investigation of the subthreshold characteristics of the ballistic
electron emission microscopy (BEEM) current in ballistic electron emission spectroscopy. Starting
from the Bell-Kaiser model, we derive an analytical equation to describe the subthreshold behavior
of the BEEM current. It is found that the BEEM current in this region should exhibit a subthreshold
swing of �60 mV/decade at room temperature, which we experimentally verified. This finding
provides a rule of thumb for the detectability of the subthreshold behavior in a spectrum. For spectra
where the subthreshold behavior is discernible above the signal noise, it is demonstrated that
significant deviations in the near-threshold region can occur when fitting with a simple quadratic
model that ignores the subthreshold behavior. To take the subthreshold behavior into account, a
simple analytical model is proposed. This model not only fits significantly better in the near threshold
region than the square model, but also gives a barrier height closer to the one extracted from the
Bell-Kaiser model. More significantly, this model provides a quick method to estimate the
subthreshold BEEM current amplitude based on the BEEM current above the barrier height
Journal of Applied Physics 01/2012; 111:13701. · 2.17 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The study of scanning tunneling microscopy (STM) induced localized dielectric degradation and polarity dependent breakdown (BD) in HfO 2 /SiO x dielectric stacks is presented in this work, together with a correlated investigation of the BD locations by transmission electron microscopy (TEM). The localized dielectric BD events are also analysed using conductive-atomic force microscopy (C-AFM). The analysis of the degradation and breakdown phenomenon has been performed from a macroscopic (device) level to a localized nanometer scale BD location. A new technique is adopted to induce the degradation and BD of the HfO 2 /SiO x dielectric stack locally using a combined STM/scanning electron microscopy nano-probing system. The BD locations were identified on blanket wafers and gate electrode area of the dielectric, and the sample containing these regions was prepared using focused ion beam for the physical analysis using TEM. This method of analysis is very useful in studying the nature of the BD events in dielectrics with and without the gate electrode, elucidating the role of the gate electrode in dielectric BD events.
IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singaopre; 01/2012
-
[show abstract]
[hide abstract]
ABSTRACT: The influence of stress migration (SM) on the electromigration (EM) reliability is studied here for very fine line interconnects, fabricated using the 45-nm Cu/low-κ interconnect process flow. As opposed to the current understanding that SM is not a concern for the narrow metal lines because of limited availability of vacancies for voiding, we found that SM does have serious wear-out effects. The EM lifetime distribution was severely degraded by around 38% for the samples that had been subjected to a 1000-h SM-only test, with a drastic reduction in the slope of the EM lognormal fitting distribution, from 0.548 to 0.193. The current density exponent of Black’s equation for SM+EM stressed samples is ∼1, suggesting that void had already been nucleated because of the SM-only test. The high intrinsic tensile stress in the line is suspected to be responsible for this early void nucleation. In the second part, we developed a Monte Carlo simulation model to estimate the void nucleation and growth time using the EM-only and SM+EM degradation tests. We found that at low percentile failures overall failure time is mainly growth dominated, whereas at high percentile failures overall failure time is nucleation dominated. Stress migration was found to shorten the nucleation time for all the samples.
Journal of Applied Physics 10/2011; 110(8):083702-083702-5. · 2.17 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We propose the use of high-oxygen-solubility metalgate electrodes as a material of choice for high- gate stacks in order to prolong the time-dependent-dielectric-breakdown (BD) reliability. Our findings on n-channel metal-oxide-semiconductor devices with these gate electrodes reveal that the application of low negative bias stress after a soft-BD (SBD) event helps to restore the oxygen ions and passivate the oxygen vacancy traps that comprise the percolation path. This can be a simple yet effective designfor-reliability tool to initiate the self-repair of the percolation path and operate the circuit for a prolonged period after repair. The only requirement for achieving this SBD reversibility is to choose gate electrodes that can serve as good oxygen reservoirs.
IEEE Electron Device Letters 04/2011; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.
Applied Physics Letters 02/2011; 98(7):072902-072902-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We modify the existing oxide breakdown (BD) percolation model in this letter to account for the presence of microstructural weakest link grain boundary (GB) defects in polycrystalline high-κ (HK) gate stacks. The different rates of the stress-induced leakage current degradation and oxide trap generation at the bulk and GB regions need to be accounted for in modeling the statistical nature of BD in HK dielectric thin films. Simulated results reveal the dominance of GB-related failures and the origin of the non-Weibull stochastics inherent in polycrystalline HK stacks. We also point to the inability of conventional percolation models with an assumed uniform defect generation to describe the failure statistics of current HK gate stacks.
IEEE Electron Device Letters 02/2011; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.
Journal of Applied Physics 01/2011; 109(1):013716-013716-9. · 2.17 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The resistive switching mechanism, which is crucial for the operations of resistive random access memory (RRAM) devices, is investigated using HfO2 based MOSFETs. After the SET operation, MOSFETs exhibit a threshold voltage (VT) shift that is found to be closely related to the formation of conductive filaments in the gate oxide. The RESET operation performed through a forming gas anneal treatment is found to have the same effect of applying a reverse polarity gate voltage sweep, as usually done in bipolar switching RRAM devices. After RESET, the gate current and VT measured shift back to their pristine levels, indicating the passivation of oxygen vacancies (forming the conductive path) as the most likely physical mechanism responsible for RRAMs RESET operation. Transmission electron microscopy analysis and physical simulations support these conclusions.
Applied Physics Letters 01/2011; 99:232909. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Vertically arrayed Si nanowire/nanorod-based core-shell p-n junction solar cells have been fabricated by a solid-state phosphorus diffusion to convert the shell of the boron-doped p-type Si nanowires to n-type, thus forming a core-shell p-n junction structure. The nanowires with a nanosphere defined diameter were fabricated by an Au-film assisted electrochemical etching method, enabling controlled junction formation. The Si nanowire arrays show superior optical properties over a wide range of spectrum. In addition, longer nanowires are more effective for light trapping and absorption which is more advantageous for efficient energy harvesting. The cells show a high energy conversion efficiency of 1.47%, a significant improvement from the previously reported Si nanowire-based core-shell junction solar cells where the core-shell junctions were formed by an oppositely doped Si deposition on preformed Si nanowires. The relatively high efficiency might be mainly attributed to the extremely low reflectivity of the nanowire arrays for efficient energy harvesting and a pristine junction formation by the diffusion method.
Journal of Applied Physics 12/2010; 108(12):124303-124303-5. · 2.17 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The spatial distribution of chemical elements is studied in high-κ, metal-gated stacks applied in field effect transistors. Using the transmission electron microscope (TEM)-based analytical techniques electron energy-loss spectroscopy (EELS) and energy-dispersive x-ray spectroscopy, it is demonstrated that Al2O3 and La2O3 capping layers show distinctly different diffusion profiles. The importance of the EELS collection angle is discussed. Popular chemical distribution models that assume La-rich interface layers are rejected.
Applied Physics Letters 09/2010; 97(10):103504-103504-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS), scanning tunneling microscopy (STM) and ballistic-electron-emission microscopy (BEEM) to study the morphology and chemical nature of nanosize structural defects formed in the dielectrics across the different phases of the overall degradation process. The correlation study between the localized physical changes in the material associated with a breakdown path and the electrical characteristics of the device in the post-BD regime is realized by the ultimate resolving power of the high resolution nanoscale physical characterization tools. Various physical defects associated with the trap generation, percolation path formation and post-breakdown wear-out of the dielectric material are identified and studied. The influence and extent of the different types of defects that are responsible for various unique gate current leakage signatures such as random telegraphic noise (RTN), digital-to-analog breakdown transition, switching of percolation conduction and ultrafast transient failure owing to filamentation are reviewed. The implications of the physical studies on the feasibility of advanced high-κ metal gate stacks are also addressed.
Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the; 08/2010
-
[show abstract]
[hide abstract]
ABSTRACT: Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using suitable statistical models. Direct extension of the simple statistical model used for SiON to the HK is complicated by the presence of the interfacial sub-oxide layer (IL, SiO<sub>x</sub>) which is sandwiched between the HK and Si substrate. Given the dual-layer HK-IL dielectric stack, it is necessary to develop new statistical models and electrical test algorithms that can enable us to decode the reliability and Weibull slope of the individual HK and IL layers so that the relative reliability of these two layers can be studied to identify the layer which serves as a “savior” in prolonging the front end reliability of current HK based logic devices. In this study, we propose a new cumulative damage statistical model in conjunction with a two step voltage stress electrical test algorithm for sequential HK-IL breakdown which enables us to analyze the TDDB reliability of HK and IL separately.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
-
G. Bersuker,
D. Heh,
C.D. Young,
L. Morassi,
A. Padovani,
L. Larcher,
K.S. Yew,
Y.C. Ong,
D.S. Ang, K.L. Pey,
W. Taylor
[show abstract]
[hide abstract]
ABSTRACT: A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO<sub>2</sub> layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
-
[show abstract]
[hide abstract]
ABSTRACT: In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO<sub>2</sub>) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address while introducing high-κ at the front end. In this study, we analyze in-depth the reliability aspect of high-κ dielectrics focusing on both the time-dependent-dielectric breakdown (TDDB) and the post breakdown evolution stage. Electrical characterization, physical failure analysis, statistical reliability modeling as well as atomistic simulations have all been used to achieve a comprehensive understanding of the physics of failure in HK and the associated microstructural defects and failure mechanisms. The role played by different gate materials ranging from poly-Si → FUSI → metal gate and different HK materials (HfO<sub>2</sub>, HfSiON, HfZrO<sub>4</sub>) is also investigated. Based on the results obtained, we emphasize the need and propose a few approaches of design for reliability (DFR) in high-κ gate stacks.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, the mechanism and physics governing the breakdown and recovery in metal-gated high-κ (MG-HK) dielectric stacks is investigated. Postbreakdown recovery is observed in NiSi and TiN-gated, but not TaN-gated, HfO2-based logic devices in voltage-stress tests. Failure analysis studies reveal that metal-filamentation, besides oxygen vacancies, is responsible for the breakdown of these MG-HK dielectrics. First-principle studies show that the 5d orbitals of Hf and migrated metal atoms in the filamentation process reduce the band gap and increase the leakage current, eventually causing percolative breakdown of the dielectric. Postbreakdown recovery is feasible only for gate stacks with a low enough defect formation energy, which can be realized by selecting appropriate gate electrode materials, such as NiSi and TiN.
Applied Physics Letters 05/2010; 96(20):202903-202903-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We study the influence of multiple oxygen vacancy traps in the percolated dielectric on the postbreakdown random telegraph noise (RTN) digital fluctuations in HfO2-based metal-oxide-semiconductor transistors. Our electrical characterization results indicate that these digital fluctuations are triggered only beyond a certain gate stress voltage. First-principles calculations suggest the oxygen vacancies to be responsible for the formation of a subband in the forbidden band gap region, which affects the triggering voltage (VTRIG) for the RTN fluctuations and leads to a shrinkage of the HfO2 band gap.
Applied Physics Letters 04/2010; 96(17):172901-172901-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We report observations of unipolar recovery of dielectric breakdown in fully silicided NiSi-gate HfSiON–SiOx bilayer dielectric based high-κ metal-insulator-semiconductor (MIS) gate stack, analogous to resistive switching in metal-insulator-metal (MIM) nonvolatile memory devices. The dependence of the recovery voltage on breakdown hardness and filament location is analyzed and the physics behind MIS recovery, governed by joule heating induced oxygen vacancy trap passivation, is explained using failure analysis and statistical investigations. The observed MIS recovery phenomenon can be a tool to design for reliability in novel metal gate high-κ gate stacks.
Applied Physics Letters 04/2010; 96(14):142901-142901-3. · 3.84 Impact Factor
-
L. Wu,
H. Y. Yu,
X. Li, K. L. Pey,
J. S. Pan,
J. W. Chai,
Y. S. Chiu,
C. T. Lin,
J. H. Xu,
H. J. Wann,
X. F. Yu,
D. Y. Lee,
K. Y. Hsu,
H. J. Tao
[show abstract]
[hide abstract]
ABSTRACT: In this paper, the thermal stability of TiN metal gate with various composition prepared by different preparation technology [(e.g., atomic layer deposition (ALD) or physical vapor deposition (PVD)] on HfO2 high-K dielectric is investigated and compared by physical and electrical analysis. After annealing of the TiN/HfO2 stack at 1000 °C for 30 s, it is observed that: (1) Nitrogen tends to out-diffuse from TiN for all the samples; (2) Oxygen from the interfacial layer (IL) between HfO2 and Si tends to diffuse toward TiN. PVD Ti-rich TiN shows a wider oxygen distribution in the gate stack, and a thinner IL than the N-rich sample. Ti penetration into HfO2 is also observed in the Ti-rich sample, which can potentially lead to the dielectric break-down. Besides, the oxygen out-diffusion can be significantly suppressed for ALD TiN compared to the PVD TiN samples.
Applied Physics Letters 03/2010; 96(11):113510-113510-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The migration of Ta atoms from a transistor gate electrode into the percolated high- κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high- κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.
Applied Physics Letters 02/2010; · 3.84 Impact Factor
