K.L. Pey

Nanyang Technological University, Tumasik, Singapore

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Publications (179)275.56 Total impact

  • Microelectronics Reliability 01/2014; · 1.14 Impact Factor
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    ABSTRACT: With complex process integration approach and severe fabrication limitations caused by introduction of new materials and diminishing process margins, there are mounting concerns with the increased failure rate at the early life cycle (e.g.<1 year operation) of product application known as infant mortality failures. A paradigm change in reliability qualification methodology aim at understanding the impact of variation on reliability is required to ensure reliability robustness. Using Electromigration (EM) as an example, this paper described a methodology where the impact of process variation on reliability is studied. A model that predicts the impact of process variation on EM sigma is also proposed which enables variation and its impact on reliability to be quantified. Using this methodology, the critical process parameters impacting reliability could be identified and controlled to ensure reliability robustness.
    Microelectronics Reliability 01/2014; · 1.14 Impact Factor
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    ABSTRACT: Grain boundaries in the polycrystalline microstructure of post-annealed high-κ (HK) dielectrics are a major limitation in the reliability of HK dielectrics used for advanced CMOS technologies. Another challenge in the field of HK dielectrics is to ensure higher drain drive current in CMOS, while maintaining low leakage current. In this work, the authors demonstrate enhanced performance of HfO2 and CeO2 dielectrics by incorporating lanthanum. The resulting stacks show promising dielectric characteristics with reduced leakage current and uniform (amorphous) crystal structure. The improved HK characteristics were shown to occur even over nanometer-length scales using scanning probe microscopy and transmission electron microscopy, in agreement with previous studies based on micron-scale device-level measurement.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 01/2014; 32(3):03D125-03D125-7. · 1.36 Impact Factor
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    ABSTRACT: Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO2 dielectric on the performance of underlying SiOx (x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiOx IL beneath the GBs and thinner HfO2 dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiOx IL.
    Microelectronics Reliability 01/2014; · 1.14 Impact Factor
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    ABSTRACT: Forming is one of the key phenomenon that governs the subsequent switchability in high-κ based resistive random access memory (RRAM) devices. The variability of subsequent switching events (voltage and resistance state), shape and size of filament, reliability of the non-volatile memory device in terms of endurance and retention as well as ultra-low power operation of the memory array all depend on the forming process in one way or the other. As a result, controllability of forming and reduction of the forming voltage is an important design activity in the RRAM technology development process. In this study, we analyze the various factors that affect the forming voltage distribution from a simulation perspective using a Kinetic Monte Carlo (KMC) based formulation of the vacancy defect evolution process in the dielectric. The impact of high-κ microstructure (grain boundaries), metal–oxide interface roughness, deposition process induced defect distribution as well as role of multi-layer dielectric films on the forming time and spread is investigated in detail. The results of the study provide guidelines for further reliability design initiatives in tightening the forming distribution.
    Microelectronics Reliability 01/2014; · 1.14 Impact Factor
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    ABSTRACT: We use the thermo-chemical model of bond breakage to investigate the degradation occurring in dual-layer SiOx/HfSiON gate dielectric stacks during low-compliance soft breakdown (BD) experiments, with the ultimate goal of identifying the first layer that degrades. Time-dependent dielectric breakdown experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based BD simulations, shows that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multilayer stack.
    IEEE Electron Device Letters 10/2013; 34(10):1289-1291. · 2.79 Impact Factor
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    ABSTRACT: Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors. This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase in the leakage current, culminating in a thermal runaway and hard breakdown. The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16 Å´ ) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo defect generation and multi-phonon trap assisted tunneling (PTAT) models. We show that the transition from the digital to the analog regime is governed by a critical voltage (VCRIT ), which determines the reliability margin in the post breakdown phase. Our results have a significant impact on the post-breakdown operational reliability of SiON and advanced high-κ–SiOx interfacial layer gate stacks, wherein the SiOx layer seems to be the weakest link for percolation event.
    Journal of Applied Physics 09/2013; 114(9):094504. · 2.21 Impact Factor
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    ABSTRACT: Development of technologies for water desalination and purification is critical to meet the global challenges of insufficient water supply and inadequate sanitation, especially for point-of-use applications. Conventional desalination methods are energy and operationally intensive, whereas adsorption-based techniques are simple and easy to use for point-of-use water purification, yet their capacity to remove salts is limited. Here we report that plasma-modified ultralong carbon nanotubes exhibit ultrahigh specific adsorption capacity for salt (exceeding 400% by weight) that is two orders of magnitude higher than that found in the current state-of-the-art activated carbon-based water treatment systems. We exploit this adsorption capacity in ultralong carbon nanotube-based membranes that can remove salt, as well as organic and metal contaminants. These ultralong carbon nanotube-based membranes may lead to next-generation rechargeable, point-of-use potable water purification appliances with superior desalination, disinfection and filtration properties.
    Nature Communications 08/2013; 4:2220. · 10.02 Impact Factor
  • IEEE Electron Device Letters 08/2013; 34(8):1053-1055. · 2.79 Impact Factor
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    ABSTRACT: We have investigated behavior of traps formed in hafnium oxide (HfO2) by electrical stress and their influence on the charge carrier transport through Si/SiO2/HfO2/poly-Si nanostructures. The traps govern the transport process assuming a capture of charge carriers followed by their ionization via the multiphonon transition mechanism. The multiphonon transitions via the Poole–Frenkel effect or electron tunneling as well as the multiphonon tunneling ionization of neutral traps have been carefully considered for charged traps. We also provide a set of parameters including the trap concentration, ionization energy, the frequency factor, the effective mass of charge carriers, optical energy, and phonon energy in order to reproduce and reasonably fit available experimental data.
    physica status solidi (a) 02/2013; 210(2):361-366. · 1.21 Impact Factor
  • N. Raghavan, K. Shubhakar, Kin Leong Pey
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    ABSTRACT: Dielectric breakdown is one of the critical failure mechanisms and showstopper for ultra-large scale integrated (ULSI) circuits as it impacts the performance and functioning of the transistor, which is the fundamental unit governing the operation of all the advanced microprocessors that we have today. As a reliability engineer, it is essential that the failure mode and mechanism be best described using statistical distributions that correlate with the physical mechanism and driving forces causing failure. In many cases, the distributions used to represent the time to failure data are empirically assumed, without carefully considering its implications on the extrapolated predictions of field lifetime. Application of a wrong distribution can give lifetime estimates that vary by many orders of magnitude, which nullify the very purpose of the reliability study in itself. The Weibull distribution is commonly used to describe random defect generation induced percolation failure of the oxide (dielectric) by means of the “weakest link” phenomenology [1, 2]. While the assumption of a Weibull distribution is well justified for silicon oxide (SiO2) and silicon oxynitride (SiON) materials [3, 4], the application of the same stochastics for high permittivity (high-κ) dielectrics is questionable [5] - [7]. This is fundamentally attributable to the different microstructure of the grown / deposited dielectrics, which we will discuss in detail, along with strong physical analysis evidence. We will present further evidence using Kinetic Monte Carlo (KMC) simulations to explain the origin of the non-Weibullian trends observed. The key motivation of this study is to caution microelectronics reliability scientists against the use of standard statistical distributions for all scenarios. We may have to resort to the need for non-standard distributions or selectively use the standard distributions only over confined percentile ranges, as material and dev- ce failure mechanisms become increasingly complex and interdependent in nanoscale integrated circuits.
    Reliability and Maintainability Symposium (RAMS), 2013 Proceedings - Annual; 01/2013
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    ABSTRACT: With complex process integration approaches and severe fabrication limitations caused by the introduction of new materials and diminishing process margins, there are mounting concerns over possible increased failure rate [1] at the early life cycle (e.g.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: Dopant segregated Schottky barrier (DSSB) and Schottky barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated using industry complemetary metal oxide semiconductor field effect transistor (CMOS) processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing steps on nickel silicide formation in the DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower off-current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also presented ideality factor much closer to unity and exhibited lower electron Schottky barrier height (ΦBn) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing sequence using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ˜5× and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to the 1-step DSSB VSiNW diode.
    Japanese Journal of Applied Physics 11/2012; 51(11). · 1.07 Impact Factor
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    ABSTRACT: A systematic study on silicon native oxides grown in ambient air at room temperature is carried out using ballistic electron emission microscopy. The electronic barrier height of Au/native oxide was directly measured for native oxides at different oxidation stages. While the ballistic electron transmission decreases with increasing oxidation time, the electronic barrier height remains the same, even after oxidation for 1 week. After oxidation for 26 months, the oxide layer showed the bulk-like SiO2 barrier; however, some local areas still show the same barrier height as that of an Au/n-Si device. This demonstrates the non-uniformity of native oxide growth.
    Journal of Applied Physics 03/2012; 111(4):054111. · 2.21 Impact Factor
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    ABSTRACT: Atomic force microscopy was employed to characterize the morphological modifications induced by laser annealing of preamorphized silicon. Laser irradiation was performed at different fluence with fixed pulse durations of 23 ns. In all cases, the laser fluence used is above the threshold fluence that is needed to melt the preamorphized layer. Roughness measurements show that the surface roughness of the silicon samples increases when the laser fluence increases. Since the laser anneal was performed in air, the changes in morphology may be associated with the surface oxide formed. When a high fluence was employed, the extension of melting was sufficient to remove all surface features of the as-implanted sample but apparently there was not enough time to completely redistribute the material upon solidification. As a result, ripple-like periodic structures are formed on the surface. Therefore, a low laser fluence should be used whenever possible in the annealing of silicon samples.
    Surface Review and Letters 01/2012; 08(05). · 0.28 Impact Factor
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    ABSTRACT: We report upon a comprehensive investigation of the subthreshold characteristics of the ballistic electron emission microscopy (BEEM) current in ballistic electron emission spectroscopy. Starting from the Bell-Kaiser model, we derive an analytical equation to describe the subthreshold behavior of the BEEM current. It is found that the BEEM current in this region should exhibit a subthreshold swing of �60 mV/decade at room temperature, which we experimentally verified. This finding provides a rule of thumb for the detectability of the subthreshold behavior in a spectrum. For spectra where the subthreshold behavior is discernible above the signal noise, it is demonstrated that significant deviations in the near-threshold region can occur when fitting with a simple quadratic model that ignores the subthreshold behavior. To take the subthreshold behavior into account, a simple analytical model is proposed. This model not only fits significantly better in the near threshold region than the square model, but also gives a barrier height closer to the one extracted from the Bell-Kaiser model. More significantly, this model provides a quick method to estimate the subthreshold BEEM current amplitude based on the BEEM current above the barrier height
    Journal of Applied Physics 01/2012; 111:13701. · 2.21 Impact Factor
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    ABSTRACT: Ballistic electron emission spectroscopy (BEES) was used to determine the electron barrier height at the interface of Au and an oxidized GaAs film. Two thresholds were observed in the spectra. In a two-step procedure, we identified the first threshold at ∼1.4 eV, which we show arose from electron-hole pairs excited by photons emitted during scanning tunneling microscopy (STM), and the second threshold at ∼3.55 eV, which is attributed to the Au/oxidized-GaAs barrier. Our results demonstrate that the two-threshold behavior observed in BEES studies on metal/oxide samples is amenable to a physical model comprising of STM photocurrent and a metal/oxide interface barrier.
    Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 01/2012; 30(1):1805-. · 1.36 Impact Factor
  • Kin Leong Pey, N. Raghavan, Xing Wu, W. Liu, M. Bosman
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    ABSTRACT: Dielectric breakdown is a well documented phenomenon studied for logic transistors using SiO2/SiON and HfO2 as the oxide material with thickness ranging from 1-5 nm. Recovery of dielectric breakdown has also been reported recently and its implications on the prolonged time dependent dielectric breakdown (TDDB) lifetime are very significant. Similarly, in the non-volatile memory arena, orders of magnitude change in conductance of the oxide has been observed for different voltage levels, voltage polarities and current densities, which is commonly referred to as “resistive switching”. Interestingly, although the gate stacks used for logic and memory applications are very similar in the materials used and dimensions as well, the mechanisms postulated to explain the breakdown-recovery mechanism in logic and switching mechanism in memory are very different. Often, the mechanism underlying switching tends to be very speculative without any convincing physical and electrical evidence that confirms the underlying kinetics of the reversible conductance state transition process. The issue stems from the fact that researchers in logic and memory operate in two distinct domains and seldom interact with each other and as a result, the link between the devices used for these two applications is not clearly recognized by most scientists. In this study, we will bridge the gap between these two phenomena and take advantage of our understanding of dielectric breakdown and recovery to convincingly explain the fundamental physics governing the switching process.
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on; 01/2012
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    ABSTRACT: The effect of surface contamination on the electron tunneling in the high bias range is investigated from the perspective of ballistic electron emission microscopy (BEEM). A comparative BEEM study on the Au/SiO2/Si devices shows that there is a significant difference in the high bias range between the experiments performed with in situ and ex situ deposited Au. Detailed studies show that the difference arises from the contaminations during air exposure. These contaminations significantly accelerated the material transfer between the tip and the sample during tunneling and lead to the unreliability of BEEM studies in the high bias range on the ex situ prepared sample.
    Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 01/2012; 30(4):041402-041402-5. · 1.43 Impact Factor
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    ABSTRACT: The study of scanning tunneling microscopy (STM) induced localized dielectric degradation and polarity dependent breakdown (BD) in HfO 2 /SiO x dielectric stacks is presented in this work, together with a correlated investigation of the BD locations by transmission electron microscopy (TEM). The localized dielectric BD events are also analysed using conductive-atomic force microscopy (C-AFM). The analysis of the degradation and breakdown phenomenon has been performed from a macroscopic (device) level to a localized nanometer scale BD location. A new technique is adopted to induce the degradation and BD of the HfO 2 /SiO x dielectric stack locally using a combined STM/scanning electron microscopy nano-probing system. The BD locations were identified on blanket wafers and gate electrode area of the dielectric, and the sample containing these regions was prepared using focused ion beam for the physical analysis using TEM. This method of analysis is very useful in studying the nature of the BD events in dielectrics with and without the gate electrode, elucidating the role of the gate electrode in dielectric BD events.
    IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA); 01/2012

Publication Stats

691 Citations
275.56 Total Impact Points

Institutions

  • 2002–2013
    • Nanyang Technological University
      • • Microelectronics Centre (MEC)
      • • School of Electrical and Electronic Engineering
      Tumasik, Singapore
  • 2012
    • Singapore University of Technology and Design
      Singapore
  • 2010
    • Singapore Institute of Manufacturing Technology (SIMTech)
      Tumasik, Singapore
  • 2009
    • Massachusetts Institute of Technology
      • Department of Materials Science and Engineering
      Cambridge, MA, United States
  • 2002–2008
    • Singapore-MIT Alliance
      Cambridge, Massachusetts, United States
  • 2007
    • University of Barcelona
      Barcino, Catalonia, Spain
  • 2002–2007
    • Nanyang Normal University
      Nan-yang-shih, Henan Sheng, China
  • 2001–2002
    • National University of Singapore
      • • Department of Materials Science and Engineering
      • • Department of Electrical & Computer Engineering
      Singapore, Singapore
  • 1996
    • Institute of Microelectronics
      Tumasik, Singapore