K.L. Pey

Singapore University of Technology and Design, Singapore

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Publications (193)310.79 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: The performance of polycrystalline and amorphous germanium (Ge) as anode active materials for lithium-ion batteries was studied systematically. Polycrystalline Ge on vertically-aligned multiwall carbon nanotube (MWCNT) arrays (MWCNT/c-Ge) and amorphous Ge on the arrays (MWCNT/a-Ge) were fabricated using a low pressure chemical vapor deposition system and a radio frequency sputtering system, respectively. The vertically-aligned MWCNT arrays were used as a platform to minimize pulverization problem. The MWCNT/a-Ge had a specific capacity of 1096.1 mA hg(-1) at the rate of 162.4 mA g(-1) at the 100th cycle. In comparison, the MWCNT/c-Ge only showed a specific capacity of 730.2 mA hg(-1) at the rate of 162.4 mA g(-1) at the 100th cycle. The MWCNT/a-Ge sample showed better performances as the MWCNT/a-Ge skipped the electrochemically-driven solid-state amorphization of crystalline Ge during the first lithiation.
    Carbon 10/2014; 77:551-559. DOI:10.1016/j.carbon.2014.05.060 · 6.16 Impact Factor
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    ABSTRACT: Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO2 dielectric on the performance of underlying SiOx (x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiOx IL beneath the GBs and thinner HfO2 dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiOx IL.
    Microelectronics Reliability 09/2014; 54(9-10). DOI:10.1016/j.microrel.2014.07.154 · 1.43 Impact Factor
  • Nagarajan Raghavan · Daniel D. Frey · Kin Leong Pey
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    ABSTRACT: Noise is a key indicator of the physical phenomenon underlying device operation, defect density and degradation trends. The analysis of noise in the frequency domain and the exponent (value of slope, α on logarithmic scale) of the power spectral density (PSD) can provide useful insight on the operating and failure mechanism of any device/system. We shall use this noise as a prognostic indicator to detect the instant at which the retention loss of a non-volatile memory device begins to occur. A qualitative perspective to prognostic management of a resistive random access memory (RRAM) device is provided in this work. Our method of detecting retention loss involves the unique observation of a slope of α = 3/2, which arises due to diffusion or ionic migration phenomenon.
    Microelectronics Reliability 09/2014; 54(9-10):1729-1734. DOI:10.1016/j.microrel.2014.07.072 · 1.43 Impact Factor
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    ABSTRACT: Forming is one of the key phenomenon that governs the subsequent switchability in high-κ based resistive random access memory (RRAM) devices. The variability of subsequent switching events (voltage and resistance state), shape and size of filament, reliability of the non-volatile memory device in terms of endurance and retention as well as ultra-low power operation of the memory array all depend on the forming process in one way or the other. As a result, controllability of forming and reduction of the forming voltage is an important design activity in the RRAM technology development process. In this study, we analyze the various factors that affect the forming voltage distribution from a simulation perspective using a Kinetic Monte Carlo (KMC) based formulation of the vacancy defect evolution process in the dielectric. The impact of high-κ microstructure (grain boundaries), metal–oxide interface roughness, deposition process induced defect distribution as well as role of multi-layer dielectric films on the forming time and spread is investigated in detail. The results of the study provide guidelines for further reliability design initiatives in tightening the forming distribution.
    Microelectronics Reliability 08/2014; 54(9-10). DOI:10.1016/j.microrel.2014.07.118 · 1.43 Impact Factor
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    ABSTRACT: With complex process integration approach and severe fabrication limitations caused by introduction of new materials and diminishing process margins, there are mounting concerns with the increased failure rate at the early life cycle (e.g.<1 year operation) of product application known as infant mortality failures. A paradigm change in reliability qualification methodology aim at understanding the impact of variation on reliability is required to ensure reliability robustness. Using Electromigration (EM) as an example, this paper described a methodology where the impact of process variation on reliability is studied. A model that predicts the impact of process variation on EM sigma is also proposed which enables variation and its impact on reliability to be quantified. Using this methodology, the critical process parameters impacting reliability could be identified and controlled to ensure reliability robustness.
    Microelectronics Reliability 08/2014; 54(9-10). DOI:10.1016/j.microrel.2014.07.096 · 1.43 Impact Factor
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    ABSTRACT: Nickel oxide (NiO) directly grown on nickel foam is regarded as a promising lithium ion battery anode material which shows good cyclic and rate performances with a theoretical specific capacity of 718 mA h g− 1. In this study, we demonstrated a carbon-incorporated NiO anode (NiO–C) with a capacity per unit area of 2.11 mA h cm− 2 and 1.76 mA h cm− 2 at 0.2 C and 0.5 C rates, respectively, fabricated by thermal oxidation of carbon coated nickel foam. The specific capacity of our NiO–C composite samples at 0.5 C rate is found to be typically 389.16 mA h g− 1, with a stable cyclic performance up to more than 100 cycles. This remarkable performance is apparently superior to the control samples of pure NiO samples. The improved performance is contributed to carbon incorporation which serves as a fluent channel for electrons and a flexible network preventing NiO nanostructures from structural deformation during charge and discharge processes. The advantage of using our approach is the easy preparation of the NiO–C composite using a simple two-step process: chemical vapor deposition of ethanol and annealing in air.
    Thin Solid Films 05/2014; 558. DOI:10.1016/j.tsf.2014.01.087 · 2.13 Impact Factor
  • Nagarajan Raghavan · Kin Leong Pey · Kalya Shubhakar
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    ABSTRACT: Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO2-based high-kappa dielectrics replacing SiO2 and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness similar to 1-2 nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-x gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.
    Microelectronics Reliability 05/2014; 54(5). DOI:10.1016/j.microrel.2014.02.013 · 1.43 Impact Factor
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    ABSTRACT: Grain boundaries in the polycrystalline microstructure of post-annealed high-κ (HK) dielectrics are a major limitation in the reliability of HK dielectrics used for advanced CMOS technologies. Another challenge in the field of HK dielectrics is to ensure higher drain drive current in CMOS, while maintaining low leakage current. In this work, the authors demonstrate enhanced performance of HfO2 and CeO2 dielectrics by incorporating lanthanum. The resulting stacks show promising dielectric characteristics with reduced leakage current and uniform (amorphous) crystal structure. The improved HK characteristics were shown to occur even over nanometer-length scales using scanning probe microscopy and transmission electron microscopy, in agreement with previous studies based on micron-scale device-level measurement.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 05/2014; 32(3):03D125-03D125-7. DOI:10.1116/1.4876335 · 1.36 Impact Factor
  • K. Shubhakar · N. Raghavan · K. L. Pey
    01/2014; DOI:10.12720/ijmse.2.2.81-86
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    ABSTRACT: We use the thermo-chemical model of bond breakage to investigate the degradation occurring in dual-layer SiOx/HfSiON gate dielectric stacks during low-compliance soft breakdown (BD) experiments, with the ultimate goal of identifying the first layer that degrades. Time-dependent dielectric breakdown experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based BD simulations, shows that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multilayer stack.
    IEEE Electron Device Letters 10/2013; 34(10):1289-1291. DOI:10.1109/LED.2013.2275182 · 3.02 Impact Factor
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    ABSTRACT: Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors. This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase in the leakage current, culminating in a thermal runaway and hard breakdown. The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16 Å´ ) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo defect generation and multi-phonon trap assisted tunneling (PTAT) models. We show that the transition from the digital to the analog regime is governed by a critical voltage (VCRIT ), which determines the reliability margin in the post breakdown phase. Our results have a significant impact on the post-breakdown operational reliability of SiON and advanced high-κ–SiOx interfacial layer gate stacks, wherein the SiOx layer seems to be the weakest link for percolation event.
    Journal of Applied Physics 09/2013; 114(9):094504. DOI:10.1063/1.4819445 · 2.19 Impact Factor
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    ABSTRACT: Development of technologies for water desalination and purification is critical to meet the global challenges of insufficient water supply and inadequate sanitation, especially for point-of-use applications. Conventional desalination methods are energy and operationally intensive, whereas adsorption-based techniques are simple and easy to use for point-of-use water purification, yet their capacity to remove salts is limited. Here we report that plasma-modified ultralong carbon nanotubes exhibit ultrahigh specific adsorption capacity for salt (exceeding 400% by weight) that is two orders of magnitude higher than that found in the current state-of-the-art activated carbon-based water treatment systems. We exploit this adsorption capacity in ultralong carbon nanotube-based membranes that can remove salt, as well as organic and metal contaminants. These ultralong carbon nanotube-based membranes may lead to next-generation rechargeable, point-of-use potable water purification appliances with superior desalination, disinfection and filtration properties.
    Nature Communications 08/2013; 4:2220. DOI:10.1038/ncomms3220 · 10.74 Impact Factor
  • Nagarajan Raghavan · Xing Wu · Michel Bosman · Kin Leong Pey
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    ABSTRACT: Voltage-induced recovery of dielectric breakdown is a well known phenomenon that has recently been proposed as an effective technique to rejuvenate nanoscale device performance and enhance the reliability lifetime of ultrathin high-k. gate stacks. Considering that most of the circuits at operating conditions take years to suffer soft breakdown (BD) as estimated by extrapolation models, it would be potentially useful to probe whether the pre-BD defect generation-induced time-dependent leakage evolution of the dielectric, commonly referred to as the stress-induced leakage current (SILC), can be reversed permanently so that circuit performance is enhanced from time to time even before the percolation event. In this letter, we investigate the feasibility of SILC recovery in state-of-the-art sub-10-angstrom equivalent oxide thickness TiN-TaN-HfLaO-SiOx gate stacks by arresting the degradation of the dielectric using carefully chosen compliance values representative of the pre-BD regime. Our results clearly show the improvement in the saturation drive current and transfer characteristics and reduction in gate leakage and noise spectrum in the SILC stage by initiating a simple negative polarity sweep. Reversibility of SILC is attributed to the backward drift of mobile oxygen ions stored in the oxygen soluble metal gate.
    IEEE Electron Device Letters 08/2013; 34(8):1053-1055. DOI:10.1109/LED.2013.2268246 · 3.02 Impact Factor
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    ABSTRACT: We have investigated behavior of traps formed in hafnium oxide (HfO2) by electrical stress and their influence on the charge carrier transport through Si/SiO2/HfO2/poly-Si nanostructures. The traps govern the transport process assuming a capture of charge carriers followed by their ionization via the multiphonon transition mechanism. The multiphonon transitions via the Poole–Frenkel effect or electron tunneling as well as the multiphonon tunneling ionization of neutral traps have been carefully considered for charged traps. We also provide a set of parameters including the trap concentration, ionization energy, the frequency factor, the effective mass of charge carriers, optical energy, and phonon energy in order to reproduce and reasonably fit available experimental data.
    physica status solidi (a) 02/2013; 210(2):361-366. DOI:10.1002/pssa.201228083 · 1.21 Impact Factor
  • Wee Loon Ng · Yong Chiang Ee · Kin Leong Pey · Chuan Seng Tan
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    ABSTRACT: With complex process integration approaches and severe fabrication limitations caused by the introduction of new materials and diminishing process margins, there are mounting concerns over possible increased failure rate [1] at the early life cycle (e.g.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
  • N. Raghavan · K. Shubhakar · Kin Leong Pey
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    ABSTRACT: Dielectric breakdown is one of the critical failure mechanisms and showstopper for ultra-large scale integrated (ULSI) circuits as it impacts the performance and functioning of the transistor, which is the fundamental unit governing the operation of all the advanced microprocessors that we have today. As a reliability engineer, it is essential that the failure mode and mechanism be best described using statistical distributions that correlate with the physical mechanism and driving forces causing failure. In many cases, the distributions used to represent the time to failure data are empirically assumed, without carefully considering its implications on the extrapolated predictions of field lifetime. Application of a wrong distribution can give lifetime estimates that vary by many orders of magnitude, which nullify the very purpose of the reliability study in itself. The Weibull distribution is commonly used to describe random defect generation induced percolation failure of the oxide (dielectric) by means of the “weakest link” phenomenology [1, 2]. While the assumption of a Weibull distribution is well justified for silicon oxide (SiO2) and silicon oxynitride (SiON) materials [3, 4], the application of the same stochastics for high permittivity (high-κ) dielectrics is questionable [5] - [7]. This is fundamentally attributable to the different microstructure of the grown / deposited dielectrics, which we will discuss in detail, along with strong physical analysis evidence. We will present further evidence using Kinetic Monte Carlo (KMC) simulations to explain the origin of the non-Weibullian trends observed. The key motivation of this study is to caution microelectronics reliability scientists against the use of standard statistical distributions for all scenarios. We may have to resort to the need for non-standard distributions or selectively use the standard distributions only over confined percentile ranges, as material and dev- ce failure mechanisms become increasingly complex and interdependent in nanoscale integrated circuits.
    Reliability and Maintainability Symposium (RAMS), 2013 Proceedings - Annual; 01/2013
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    ABSTRACT: Dopant segregated Schottky barrier (DSSB) and Schottky barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated using industry complemetary metal oxide semiconductor field effect transistor (CMOS) processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing steps on nickel silicide formation in the DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower off-current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also presented ideality factor much closer to unity and exhibited lower electron Schottky barrier height (ΦBn) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing sequence using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ˜5× and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to the 1-step DSSB VSiNW diode.
    Japanese Journal of Applied Physics 11/2012; 51(11). DOI:10.1143/JJAP.51.11PE08 · 1.06 Impact Factor
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    ABSTRACT: The effect of surface contamination on the electron tunneling in the high bias range is investigated from the perspective of ballistic electron emission microscopy (BEEM). A comparative BEEM study on the Au/SiO2/Si devices shows that there is a significant difference in the high bias range between the experiments performed with in situ and ex situ deposited Au. Detailed studies show that the difference arises from the contaminations during air exposure. These contaminations significantly accelerated the material transfer between the tip and the sample during tunneling and lead to the unreliability of BEEM studies in the high bias range on the ex situ prepared sample.
    Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 07/2012; 30(4):041402-041402-5. DOI:10.1116/1.4721640 · 2.14 Impact Factor
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    H L Qin · K E J Goh · C Troadec · M Bosman · K L Pey
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    ABSTRACT: A systematic study on silicon native oxides grown in ambient air at room temperature is carried out using ballistic electron emission microscopy. The electronic barrier height of Au/native oxide was directly measured for native oxides at different oxidation stages. While the ballistic electron transmission decreases with increasing oxidation time, the electronic barrier height remains the same, even after oxidation for 1 week. After oxidation for 26 months, the oxide layer showed the bulk-like SiO2 barrier; however, some local areas still show the same barrier height as that of an Au/n-Si device. This demonstrates the non-uniformity of native oxide growth.
    Journal of Applied Physics 03/2012; 111(4):054111. DOI:10.1063/1.3693556 · 2.19 Impact Factor
  • Y. F.chong · K. L.pey · Y. F.lu · A. T. S.wee · A.see
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    ABSTRACT: Atomic force microscopy was employed to characterize the morphological modifications induced by laser annealing of preamorphized silicon. Laser irradiation was performed at different fluence with fixed pulse durations of 23 ns. In all cases, the laser fluence used is above the threshold fluence that is needed to melt the preamorphized layer. Roughness measurements show that the surface roughness of the silicon samples increases when the laser fluence increases. Since the laser anneal was performed in air, the changes in morphology may be associated with the surface oxide formed. When a high fluence was employed, the extension of melting was sufficient to remove all surface features of the as-implanted sample but apparently there was not enough time to completely redistribute the material upon solidification. As a result, ripple-like periodic structures are formed on the surface. Therefore, a low laser fluence should be used whenever possible in the annealing of silicon samples.
    Surface Review and Letters 01/2012; 08(05). DOI:10.1142/S0218625X01001208 · 0.37 Impact Factor

Publication Stats

1k Citations
310.79 Total Impact Points

Institutions

  • 2012–2014
    • Singapore University of Technology and Design
      • Division of Engineering Product Development
      Singapore
  • 2002–2013
    • Nanyang Technological University
      • • Microelectronics Centre (MEC)
      • • Division of Microelectronics (MI)
      • • School of Electrical and Electronic Engineering
      Tumasik, Singapore
  • 2011
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 2006–2010
    • Singapore-MIT Alliance
      Cambridge, Massachusetts, United States
  • 2007
    • University of Barcelona
      Barcino, Catalonia, Spain
    • Nanyang Normal University
      Nan-yang-shih, Henan Sheng, China
  • 2005
    • National Chiao Tung University
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2004–2005
    • INO - Istituto Nazionale di Ottica
      Florens, Tuscany, Italy
  • 1995–2004
    • Institute of Microelectronics
      Tumasik, Singapore