Harika Manem

City University of New York - Brooklyn College, Brooklyn, New York, United States

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Publications (19)20.72 Total impact

  • Proceedings of the IEEE 06/2012; 100(6). · 6.91 Impact Factor
  • Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2012; 59(5). · 2.24 Impact Factor
  • ACM Journal on Emerging Technologies in Computing Systems 02/2012; 8(1). · 0.76 Impact Factor
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    ABSTRACT: With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.
    ACM Journal on Emerging Technologies in Computing Systems - JETC. 01/2012;
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    ABSTRACT: Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. Specifically, the innate reconfigurability of memristors can be exploited to realize synapses in artificial neural networks. This work focuses on the development of a variation-tolerant training methodology to efficiently reconfigure memristive synapses in a Trainable Threshold Gate Array (TTGA) system. The training process is inspired from the gradient descent machine learning algorithm commonly used to train artificial threshold neural networks, perceptrons. The design and CMOS/Nano implementation of the TTGA system from trainable perceptron based threshold gates is detailed and results are provided to showcase the training process and performance characteristics of the proposed system. Also shown are the results for training a 1T1M (1 Transistor and 1 Memristor) multilevel memristive memory and its performance characteristics.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2012; 59(5):1051-1060. · 2.24 Impact Factor
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    ABSTRACT: Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.
    IEEE Transactions on Computers 01/2012; 61:474-487. · 1.38 Impact Factor
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    ABSTRACT: The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal–oxide–semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.
    Proceedings of the IEEE 01/2012; 100(6):2033-2049. · 6.91 Impact Factor
  • Harika Manem, Garrett S. Rose
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    ABSTRACT: Technology migration into nano and molecular scales has led to the design of several hybrid CMOS/nano logic and memory architectures that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale memory and logic systems by facilitating the implementation of multi-level logic. In this work we propose a sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit storage in each data cell (memristor). Robust read and write methodologies for the proposed architecture are also discussed and tradeoffs between faster write speeds and larger read noise margins are also analyzed. Another highlight of this work is the usage of the exponential drift memristor model to further enhance write speeds of these devices which are otherwise much slower. Index Terms—Memristor, multi-level memory, 1T1M
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: Memristors have been proposed to be used in a wide variety of applications ranging from neural networks to memory to digital logic. Like other electronic devices, memristors are also prone to process variations. We show that the effect of process induced variations in the thickness of the oxide layer of a memristor has a non-linear relationship with memristance. We analyze the effects of process variation on memristor-based threshold gates. We propose two algorithms to tolerate variations on memristance based on two different constraints. One is used to determine the memristance values for a given list of Boolean functions to tolerate a maximum amount of variation. The other is used to determine the list of Boolean functions that can tolerate a maximum amount of variation for given memristance values. Finally, we analyze the performance of memristor-based threshold gates to tolerate variations.
    VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011; 01/2011
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    ABSTRACT: In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.
    Nanoscale Architectures, IEEE International Symposium on. 01/2010;
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    ABSTRACT: With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.
    Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010; 01/2010
  • Garrett S. Rose, Harika Manem
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    ABSTRACT: Abstract From the final years of the twentieth century, nanotechnology has emerged in various forms with the promise of enabling new applications among a variety of disciplines. The field of digital integrated circuit design is one such discipline within which researchers are continually seeking ways of leveraging novel nanoscale technologies to develop next generation circuits and architectures. A major motivating factor for this research is the expected end of device scaling for more conventional bulk silicon technologies, specifically CMOS. Many nanoscale devices have been proposed as replacements for the MOS transistor, from spintronic devices to molecular switches, each coming with their own pros and cons. In fact, it can be argued that, for many applications, nanoscale CMOS remains as viable as any other nanoelectronic device family, at least in the near term. Thus, this chapter explores the concept of hybrid CMOS-nano circuit design for leveraging the best of scaled CMOS alongside of the best of novel nanoelectronics. This is accomplished by describing some novel nanoelectronic devices and comparing them to the traditional MOSFET. After some discussion about circuit level considerations when integrating CMOS with nanoelectronics, a hybrid CMOS-nano field programmable gate array (FPGA) based on nanoscale hysteretic switches and negative differential resistance (NDR) is also described and explored in detail. KeywordsVLSI-Nanoelectronics-FPGA-Majority logic
    12/2009: pages 139-161;
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    ABSTRACT: A programmable logic array (PLA) needs its inputs available in both the positive and negative polarities. In lithographic-scale VLSI PLAs, programmable array logics (PALs) and programmable logic devices (PLDs) a buffer and inverter at the PLA input typically produces both polarities from a single polarity input. However, the extreme regularity required for sublithographic designs has driven nanoscale architectures to consider alternate solutions. Consequently, the authors compare three schemes: one based on producing both polarities in a restoration stage (selective inversion), one based on a local inversion stage and one based on a full dual-rail logic implementation. The authors develop a mapping flow for the dual-rail logic and quantify its cost in both logical product terms and physical implementation area and also develop area and timing models for all three schemes. Mapping benchmarks from the Toronto 20 set, the authors are able to show that the local inversion scheme is faster (less than one-fifth the latency), lower energy (one-half the energy) and comparable size to the selective inversion scheme and faster (less than half the latency), smaller (one-third of the area) and lower energy (one-ninth the energy) than the dual-rail scheme.
    IET Computers & Digital Techniques 12/2009; · 0.28 Impact Factor
  • 11/2009; 3(6):625-642.
  • J. Rajendran, H. Manem, G.S. Rose
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    ABSTRACT: In recent years, many researchers have proposed the usage of molecular scale devices exhibiting negative differential resistance (NDR) in the realization of programmable logic circuitry. This paper deals with the utilization of one such system built from NDR based circuitry, specifically the Goto pair, in the implementation of a programmable threshold logic array (PTLA). Furthermore, the PTLA considered here uses memristors exhibiting multiple levels of resistance to provide weighted inputs to each threshold gate. Circuit level considerations for the Goto pair to be implemented as part of PTLA are discussed. An image classification application is also implemented using the proposed PTLA and simulated for functionality and performance using Cadence Spectre.
    Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on; 08/2009
  • H. Manem, G.S. Rose
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    ABSTRACT: The emergence of alternative technologies due to continued technology migration into the nanometer regime has led to the design of several novel logic and memory architectures. These architectures, in particular array based architectures built from crossbar structures, aim to achieve higher logic/memory densities with lower power consumption and acceptable delays as compared to present day CMOS technology. However crosstalk induced in these nanoscale arrays limits the minimum wire spacing realizable and thereby the logic density that can be achieved. In this work we analyze the crosstalk produced in sublithographic programmable logic array (PLA) architectures and propose an alternative layout scheme that reduces the effects of crosstalk in adjacent wires. The proposed methodology has an interleaved layout scheme with two non-overlapping out-of-phase clocks that prevent neighboring wires from transitioning simultaneously. Results presented in this paper indicate that this scheme provides for better tolerance against crosstalk than other structures proposed for sublithographic PLAs. The effects of different parasitics (i.e. coupling and decoupling capacitances from different parts of the crossbar segment) on the crosstalk induced are also analyzed.
    Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on; 01/2009
  • Harika Manem, Garrett S. Rose
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    ABSTRACT: In recent years, novel nanotechnology has been considered as an eventual replacement or extension for conventional technologies (e.g., CMOS) as they migrate to smaller scales. This work explores the use of such nanoscale devices for the development of a robust hybrid CMOS-nano field programmable gate array (FPGA). In particular, we utilize the properties of negative differential resistance (NDR) and hysteretic switching, observed from some nanoelectronic devices, in the design of an array-based logic circuit dubbed the programmable majority logic array (PMLA). The hybrid CMOS-nano FPGA system design described in this paper incorporates the area and power efficiency of the nano PMLA with the speed and robustness of CMOS. Furthermore, the effects of how logic is partitioned between the nano PMLA and CMOS are also considered.
    Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009; 01/2009
  • H. Manem, K. Dadhirao, G.S. Rose
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    ABSTRACT: Molecular scale electronics has become an attractive alternative and even extension to existing microscale technologies as they migrate to the nanoscale. With recent research in the field of molecular and nano electronics, devices such as switches and resonant tunneling diodes (RTD) have been developed which exhibit properties such as rectification, hysteresis and negative differential resistance (NDR). These devices have been utilized to realize circuits that can implement both memory and logic structures. This work revolves around the robustness of these nanoscale devices when employed in nanoelectronic programmable majority logic arrays (PMLA), programmable logic circuits based on majority logic resulting from NDR. We also show the results of corner analysis of the circuit's performance under parameter variations, and describe the behavior requirements of the aforementioned molecular devices, especially those of molecular switches, for the system to function efficiently.
    Nanotechnology, 2008. NANO '08. 8th IEEE Conference on; 09/2008
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    ABSTRACT: Recent research into molecular scale electronics has led to the realization of novel nanoscale devices that can be used to implement circuits such as what we dub Programmable Majority Logic Arrays (PMLA). A PMLA leverages two characteristics found in molecular electronic devices, hysteretic switching and negative differential resistance (NDR), in the implementation of a PLA based on majority logic. This paper deals with the integration of several nanoscale PMLA units with micro scale technologies to implement a high density FPGA architecture. One of the key contributions of this work is the interface between the top nanoscale layer and a lower CMOS layer. Two approaches are considered for interfacing these two technologies: (1) direct connection and (2) connection utilizing tapered buffers between the layers for improved delay. The intermediate tapered buffers in the second approach ensure that the variation in feature size, and hence load capacitance, from one layer to the next is not too substantial. This paper also demonstrates the potential of the PMLA FPGA from a high level perspective in terms of increased density and performance for a set of applications.
    Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008; 01/2008