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ABSTRACT: A 900-MHz single-pole double-throw (SPDT) switch with an insertion loss of 0.5 dB and a 2.4-GHz SPDT switch with an insertion loss of 0.8 dB were implemented using 3.3-V 0.35-μm NMOS transistors in a 0.18-μm bulk CMOS process utilizing 20-Ω·cm p<sup>-</sup> substrates. Impedance transformation was used to reduce the source and load impedances seen by the switch to increase the power handling capability. SPDT switches with 30-Ω impedance transformation networks exhibit 0.97-dB insertion loss and 24.3-dBm output P<sub>1dB</sub> when tuned for 900-MHz operation, and 1.10-dB insertion loss and 20.6-dBm output P<sub>1dB</sub> when tuned for 2.4-GHz operation. The 2.4-GHz switch is the first bulk CMOS switch which can be used for 802.11b wireless local area network applications.
IEEE Journal of Solid-State Circuits 02/2004; · 3.23 Impact Factor
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ABSTRACT: Two single-pole, double-throw transmit/receive switches were designed and fabricated with different substrate resistances using a 0.18-/spl mu/m p/sup $/substrate CMOS process. The switch with low substrate resistances exhibits 0.8-dB insertion loss and 17-dBm P/sub 1dB/ at 5.825 GHz, whereas the switch with high substrate resistances has 1-dB insertion loss and 18-dBm P/sub 1dB/. These results suggest that the optimal insertion loss can be achieved with low substrate resistances and 5.8-GHz T/R switches with excellent insertion loss and reasonable power handling capability can be implemented in a 0.18-/spl mu/m CMOS process.
IEEE Microwave and Wireless Components Letters 02/2003; · 1.72 Impact Factor
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ABSTRACT: 2.4-GHz CMOS low noise amplifier, mixer, local oscillator buffer,
differential power amplifier, and T/R switch for 802.11b WLAN
applications have been implemented using MOS transistors. A single chip
2.4-GHz transceiver for WLAN with integrated power amplifier, switches,
and other RF components will be possible in a 0.25-μm CMOS
technology. More importantly, it appears that the CMOS solution will be
highly competitive in the 2.4-GHz WLAN market
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002
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ABSTRACT: A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated using 3.3-V, 0.35-µm MOS transistors in a 0.18-µm CMOS process utilizing p<sup>-</sup>substrates. The switch exhibits 0.8-dB insertion loss and 17-dBm P 1dB . The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the source/drain-to-body capacitances and substrate resistances, while the high P 1dB is achieved by dc biasing the input and output nodes.
Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European; 10/2001
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ABSTRACT: A single-pole double-throw transmit/receive switch for 3.0-V
applications has been fabricated in a 0.5-μm CMOS process. An
analysis shows that substrate resistances and source/drain-to-body
capacitances must be lowered to decrease insertion loss. The switch
exhibits a 0.7-dB insertion loss, a 17-dBm power 1-dB compression point
(P<sub>1 dB</sub>), and a 42-dB isolation at 928 MHz. The low insertion
loss is achieved by optimizing the transistor widths and bias voltages,
by minimizing the substrate resistances, and by dc biasing the transmit
and receive nodes, which decreases the capacitances while increasing the
power 1-dB compression point. The switch has adequate insertion loss,
isolation, P<sub>1 dB</sub>, and IP<sub>3</sub> for a number of 900-MHz
ISM band applications requiring a moderate peak transmitter power level
(~15 dBm)
IEEE Journal of Solid-State Circuits 04/2001; · 3.23 Impact Factor
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ABSTRACT: A single-pole, double-throw transmit/receive switch for 3.0-V
applications has been fabricated in a 0.5-μm CMOS process. The switch
exhibits a 0.8-dB insertion loss and a 17-dBm P<sub>1dB</sub>. The low
insertion loss is achieved by optimizing the transistor widths and bias
voltages, and by minimizing the substrate resistances, while the high 1
dB compression point is achieved by DC biasing the input and output
nodes
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000; 02/2000
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ABSTRACT: An 0.8-/spl mu/m n-channel MOSFET with a TiSi/sub 2/-Si Schottky clamped drain-to-body junction (SCDR) and an n/sup +/ implanted standard source structure have been fabricated in a conventional 0.8-/spl mu/m salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n/sup +/-drain/p-substrate/n/sup +/-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n/sup +/ drain-to-p-substrate guard-ring diode connected in parallel.
IEEE Electron Device Letters 10/1998; · 2.85 Impact Factor
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ABSTRACT: 1.2 μm p-channel MOSFETs with a TiSi<sub>2</sub>-Si barrier
drain and a p<sup>+</sup> implanted source have been fabricated.
Parasitic drain-to-n-well-to-p<sup>+</sup>-source bipolar transistor
measurements showed no current gain since the Schottky-barrier-drain
(SBDR) does not inject minority carriers (holes) to the n-well base. The
SBDR could be useful for preventing latch-up in integrated CMOS RF
amplifiers
Electronics Letters 08/1997; · 0.96 Impact Factor
