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ABSTRACT: The effects of glycine on morphine-induced hyperactivity, reverse tolerance and postsynaptic dopamine receptor supersensitivity in mice was examined. A single administration of morphine (10 mg/kg, s.c.) induced hyperactivity as measured in mice. The morphine-induced hyperactivity was inhibited by pretreatment with glycine (100, 200 and 400 mg/kg, i.p.). In addition, it was found repeated administration of morphine (10 mg/kg, s.c.) to mice daily for 6 days caused an increase in motor activity which could be induced by a subsequent morphine dose, an effect known as reverse tolerance or sensitization. Glycine (100, 200 and 400 mg/kg, i.p.) also inhibited morphine-induced reverse tolerance. Mice that had received 7 daily repeated administrations of morphine also developed postsynaptic dopamine receptor supersensitivity, as shown by enhanced ambulatory activity after administration of apomorphine (2 mg/kg, s.c.). Glycine inhibited the development of postsynaptic dopamine receptor supersensitivity induced by repeated administration of morphine. It is suggested that the inhibitory effects of glycine might be mediated by dopaminergic (DAergic) transmission. Accordingly, the inhibition by glycine of the morphine-induced hyperactivity, reverse tolerance and dopamine receptor supersensitivity suggests that glycine might be useful for the treatment of morphine addiction.
Archives of Pharmacal Research 01/2004; 26(12):1074-8. · 1.59 Impact Factor
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ABSTRACT: Modern digital communication systems rely heavily on baseband
signal processing for in-phase and quadrature (I-Q) channels, and
complex number processing in low-voltage CMOS has become a necessity for
channel equalization, timing recovery, modulation, and demodulation. In
this work, redundant binary (RB) arithmetic is applied to complex number
multiplication for the first time so that an N-bit parallel complex
number multiplier can be reduced to two RE multiplications (i.e., an
addition of N RB partial products) corresponding to real and imaginary
parts, respectively. This efficient RE encoding scheme proposed can
generate RB partial products with no additional hardware and delay
overheads. A prototype 8-bit complex number multiplier containing 11.5 K
transistors is integrated on 1.05×1.33 mm<sup>2</sup> using 0.8
μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at
200 MHz
IEEE Journal of Solid-State Circuits 07/1998; · 3.23 Impact Factor
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ABSTRACT: A new approach for high-speed complex multiplication and its VLSI
architecture is presented. By employing redundant binary (RB)
arithmetic, an N-hit complex multiplication is reduced to a pair of N RB
partial products (RBPPs) additions. Also, an efficient RB encoding
scheme proposed in this paper enables us to generate RBPPs without
hardware and delay overheads compared to binary partial product
generation. The proposed algorithm results in a parallel architecture
that consists of two symmetric tree structures, one is responsible for
real part and the other is for imaginary part of final complex product.
Its architectural regularity results in a compact layout, and makes it
very attractive for VLSI realization. As a test vehicle, an 8-bit
complex multiplier core has been designed with 0.8 μm CMOS technology
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on; 07/1997
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ABSTRACT: This paper describes an efficient array algorithm for parallel
computation of vector-radix two-dimensional (2-D) discrete cosine
transform (VR-DCT), and its VLSI implementation. By mapping the 2-D
VR-DCT onto a 2-D array of processing elements (PEs), the DCT is
efficiently computed with high concurrency and local data exchanges
between PEs. The proposed array algorithm features architectural
modularity, regularity and locality, so that it is very suitable for
VLSI realization. Also, no transposition memory is required. It has the
time complexity of O(N+N<sub>NZD</sub>·log<sub>2</sub>N) for
(N×N) 2-D DCT, where N<sub>NZD</sub> is the number of non-zero
digits in the canonic-signed digit (CSD) representation of DCT kernel.
Based on the proposed array algorithm, an array processor for
(8×8) 2-D DCT is designed using 1.5 μm double metal CMOS
technology. From simulation results, it is estimated that (8×8)
2-D DCT (with N<sub>NZD</sub>=4) can be computed in about 0.88 μsec
at 50 MHz clock frequency, resulting in the throughput rate of about 72
Mega pixels/sec
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on; 01/1994
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ABSTRACT: An implementation of a two-dimensional array processor for fast
Fourier transform (FFT) using a 2-μm CMOS technology is presented.
The array processor, which is dedicated to 16-point FFT, implements a
4×4 mesh array of 16 processing elements (PEs) working in
parallel. Design considerations in both the chip level and the PE level
are examined. A layout design methodology based on bit-slice units
(BSUs) results in a very simple design, easy debugging, and a regular
interconnection scheme through abutment. It contains about 48,000
transistors on an area of 53.52 mm<sup>2</sup>, excluding the 83-pad
area, and operation is on a 15-MHz clock. The array processor performs
24.6 million complex multiplications per second, and computes a 16-point
FFT in 3 μs
IEEE Journal of Solid-State Circuits 10/1991; · 3.23 Impact Factor
