L. Milor

Georgia Institute of Technology, Atlanta, Georgia, United States

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Publications (100)26.07 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime due to backend dielectric breakdown is presented. It incorporates failures due to parallel tracks, the width effect, field enhancement due to line ends, and variation in activity and temperature. Different workloads are considered as well, in order to evaluate aging effects in microprocessors running real-world applications with realistic use conditions.
    Microelectronics Journal 10/2014; · 0.91 Impact Factor
  • Soonyoung Cha, Chang-Chih Chen, Linda S. Milor
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    ABSTRACT: With the scaling of CMOS technology, Negative Bias Temperature Instability (NBTI) and Process Variations (PV) are serious issues for transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a method to determine the initial average channel length (L) and threshold voltage (Vth0) for individual chips, together with NBTI model parameters through I/O measurements. We determine a relationship between ΔVth, Vth0, L and ground signal variation and fit models to the simulation results. The voltage of the ground signal is used for the calculation of the delay and amplitude shifts which are used to extract PV and NBTI parameters. Then, we calculate the lifetime for each chip individually using calibrated NBTI models, accounting for process variations. The methodology enables the extraction of NBTI and PV model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that have different parameters initially and are more or less vulnerable to NBTI.
    IEEE International Reliability Physics Symposium; 06/2014
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    ABSTRACT: Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of NBTI, PBTI and HCI on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to BTI and HCI. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime because of backend dielectric breakdown is presented. It incorporates failures because of parallel tracks, the width effect, and field enhancement due to line ends. It also includes the operating temperature and activity.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2014; 22(8):1750-1762. · 1.22 Impact Factor
  • Chang-Chih Chen, L. Milor
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    ABSTRACT: In this paper, we have developed a framework to study wearout of state-of-the-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, which are determined by running benchmarks on the system, we present a methodology to accurately estimate the lifetime due to each mechanism. The lifetime-limiting blocks and paths of a circuit are highlighted using standard benchmarks.
    Advances in Sensors and Interfaces (IWASI), 2013 5th IEEE International Workshop on; 01/2013
  • L. Milor
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    ABSTRACT: Fast yield learning is critical to bringing products to the market in a timely fashion and is strongly linked to product revenues. This paper reviews methods to enable efficient yield learning, focusing on methods to quantify the most significant yield detractors and on in-line excursion detection methodologies.
    IEEE Transactions on Semiconductor Manufacturing 01/2013; 26(2):196-213. · 0.86 Impact Factor
  • Chang-Chih Chen, Linda Milor
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    ABSTRACT: Backend wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework which contains modules for backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze circuit layout geometries and interconnects to accurately estimate state-of-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress, temperature, linewidth and cross-sectional areas of each interconnect within the microprocessor system. We analyze several layouts using our methodology and highlight the lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units, using standard benchmarks.
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013; 01/2013
  • Fahad Ahmed, Linda Milor
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    ABSTRACT: Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2012; 20(5):855-864. · 1.22 Impact Factor
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    ABSTRACT: Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.
    01/2012;
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    ABSTRACT: Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown. Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
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    ABSTRACT: In this work, we perform a comparative study of different wearout mechanisms affecting the state-of-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, we present a methodology to accurately estimate the lifetime due to each mechanism. The lifetime-limiting wearout mechanisms are highlighted using standard benchmarks along with the reliability-critical microprocessor functional units.
    Computer Design (ICCD), 2012 IEEE 30th International Conference on; 01/2012
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    ABSTRACT: form only given. Negative bias temperature instability (NBTI) is one of the important reliability concerns that most drastically impacts circuit performances. In the digital domain, NBTI is addressed through adding reliability guard-bands on the maximum operating frequency of data paths and on the noise margins for memory cells. As a result, NBTI limits the performance/area optimization of digital circuits. Similarly, NBTI in analog circuits must be modeled and analyzed to ensure reasonable product lifetimes. The analysis of NBTI for analog circuits is more complex, since statistical NBTI causes not just performance degradation, but also increasing mismatch. Hence, randomness in the degradation process must be handled properly for analog circuits. In this work, we present a methodology to determine the impact of statistical NBTI on analog circuits. NBTI is due to the presence of interface traps at the gate oxide interface. It causes the threshold of PMOS devices to change.
    Test Symposium (ETS), 2012 17th IEEE European; 01/2012
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    ABSTRACT: Backend dielectric breakdown is one of the major sources of wearout for microprocessors. We present test data and a methodology to accurately estimate the lifetime for a microprocessor system due to backend dielectric breakdown. Our methodology incorporates activity in the nets surrounding each dielectric segment in the layout, temperature, and all layout spacings among parallel tracks. We analyze several layouts using our methodology and show the impact of backend dielectric wearout on microprocessor system lifetime.
    Microelectronics Reliability 01/2012; 52(s 9–10):1953–1959. · 1.14 Impact Factor
  • Z. LV, L. Milor, S. Yang
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    ABSTRACT: The faults caused by process variation and degradation are different, which makes it difficult to handle reliability. This paper proposes a statistical model of NBTI, which captures all the variations that come from circuit use conditions, and presents a framework to do analogue reliability simulations, with which reliability can be handled as early as the design phase. A feed-forward equalizer (FFE) was studied. For this circuit, we have found the limiting performances for reliability, which helps to enable the design of on-line tests for reliability.
    Microelectronics Reliability 01/2012; 52(s 9–10):1837–1842. · 1.14 Impact Factor
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    ABSTRACT: Backend low-k time-dependent dielectric breakdown degrades reliability of circuits with Copper metallization. We present test data and link it to a methodology to evaluate chip lifetime due to low-k time-dependent dielectric breakdown. Other failure mechanisms can be integrated into our methodology. We analyze several layouts using our methodology and present the results to show that the methodology can enable the designer to consider easy design modifications and their impact on lifetime, separate from the design rules.
    Reliability Physics Symposium (IRPS), 2011 IEEE International; 05/2011
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    ABSTRACT: Backend geometries on chips contain a wide variety of features. We are developing a full-chip reliability simulator for low-k dielectric breakdown that takes into account the vulnerable area, linewidth, vias, and line edge roughness. The simulator provides a link between test structure results and predictions of chip dielectric lifetime. However, these factors may not be sufficient for large chips with a wider variety of features. In this paper, we analyze data from backend dielectric test structures with irregular geometries to determine if more layout features need to be added to a full-chip reliability simulator for low-k dielectric breakdown.
    Microelectronics Reliability. 01/2011; 51:1582-1586.
  • M.M. Bashir, L. Milor
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    ABSTRACT: This paper aims to develop a method to determine the impact of within-die variation in transistors on circuit timing, separately from die-to-die variation. To do this, we find a set of corners that detect all critical paths due to within-die variation. Hence, a finite number of simulations is used to explore the impact within-die variation.
    IEEE Transactions on Semiconductor Manufacturing 01/2011; 24(3):385-391. · 0.86 Impact Factor
  • Fahad Ahmed, Linda Milor
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    ABSTRACT: Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
    01/2011;
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    ABSTRACT: Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.
    Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International; 11/2010
  • Fahad Ahmed, Linda Milor
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    ABSTRACT: This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).
    Microelectronics Journal 11/2010; · 0.91 Impact Factor

Publication Stats

872 Citations
26.07 Total Impact Points

Institutions

  • 2005–2014
    • Georgia Institute of Technology
      • School of Electrical & Computer Engineering
      Atlanta, Georgia, United States
  • 2008
    • Synopsys
      Mountain View, California, United States
  • 2004
    • University of Texas at Austin
      • Department of Electrical & Computer Engineering
      Port Aransas, TX, United States
  • 1997–2002
    • University of California, Berkeley
      • Department of Electrical Engineering and Computer Sciences
      Berkeley, MO, United States
  • 1997–1999
    • Carnegie Mellon University
      • Department of Electrical and Computer Engineering
      Pittsburgh, PA, United States
    • AMD
      Sunnyvale, California, United States
    • Advanced Micro Devices
      Sunnyvale, California, United States
  • 1990–1998
    • University of Maryland, College Park
      • Department of Electrical & Computer Engineering
      College Park, MD, United States