-
[show abstract]
[hide abstract]
ABSTRACT: The noise mechanisms at high frequencies in MOSFETs are analyzed and an analytical model is presented for devices operating at gigahertz frequencies. The proposed model is applied to floating body silicon-on-insulator (SOI) as well as bulk-silicon MOS transistors and experimentally verified. The model accounts for the mechanisms of 1) channel thermal noise; 2) shot-noise due to impact ionization; and 3) substrate back-gate-coupled thermal noise. Compact, closed-form analytical expressions of the noise power spectral density and the minimum noise figure (NF) are presented. At the same technology level, the experimental data and the model show that SOI MOSFETs are able to attain lower NF than bulk-silicon devices by reduction of the back-gate transconductance. However, the higher drain electric field in the SOI, and the parasitic bipolar action and floating body enhance impact-ionization-associated shot-noise, which becomes the limiting noise mechanism at drain voltages higher than the drain onset voltage of ldquokinkrdquo effect. A correlation between the onset voltage and the DC electrical characteristics is shown.
IEEE Transactions on Electron Devices 04/2008; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The MOSFET parameters important for RF application at GHz
frequencies: a) transition frequency, b) noise figure, and c) linearity
are analyzed and correlated with substrate type. This work demonstrates
that, without process changes, high-resistivity silicon-on-insulator
(high-ρ SOI) substrates can successfully enhance the RF performance
of on-chip inductors and fully depleted (FD)-SOI devices in terms of
reducing substrate losses and parasitics. The linearity limitations of
the SOI low-breakdown voltage and "kink" effect are addressed by
judicious device and circuit design. Criteria for device optimization
are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise
amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise
figure for applications in the L and S-bands
IEEE Transactions on Electron Devices 06/2002; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The electromagnetic isolation and coupling characteristics of basic structures, namely metal pads, spiral inductors, and spiral-transistors, implemented in a core-logic CMOS process are evaluated and modeled. The models provide design guidelines on the isolation characteristics of guard-rings and shield layers for RF cross-talk suppression between circuit blocks. The importance of electromagnetic coupling to layout interconnects is demonstrated
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002
-
[show abstract]
[hide abstract]
ABSTRACT: The tradeoffs in the ESD protection device for RFCMOS circuits are described, and the characteristics of an SCR-based ESD structure are presented. The parasitic capacitance of the ESD structure is reduced to ~150 fF. 3 kV HBM and 750 V CDM are achieved in a LNA working at 2.5 GHz with NF<4dB, applicable for Bluetooth wireless transceiver
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002
-
[show abstract]
[hide abstract]
ABSTRACT: In this work, an analytical model of the OFF-state leakage current
in metal-oxide-semiconductor (MOS) transistors and its relation with the
standby current of logic complementary MOS (CMOS) ICs is presented. The
OFF leakage currents in (1) bulk MOS; (2) floating-body
silicon-on-insulator (FB-SOI); and (3) body-tied SOI (BT-SOI) MOS field
effect transistors (MOSFETs) are modeled based on physics mechanisms,
equivalent circuits and operational block diagrams. Good correlation is
obtained between the theory and experimental devices. The model
clarifies and quantifies that in thin film FB-SOI, the OFF leakage
current is dominated by (a) V<sub>th</sub> at drain voltages lower than
the onset of the “kink” effect V<sub>ds</sub><V<sub>dk
</sub>, and (b) the impact ionization-induced floating-body effect for V
<sub>ds</sub>>V<sub>dk</sub>. The OFF-state leakage current model is
successfully applied to the analysis and prediction of the leakage
current components in logic integrated circuits (CMOS ICs)
IEEE Transactions on Electron Devices 10/2001; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Recently, CMOS has been actively developed for RF applications in the low-GHz range. Full integration of the RF active and passive components in bulk-Si however, requires special processing, like triple well and deep trenches to control the cross-talk interaction, substrate noise and Q-factor degradation of on-chip inductors (Erzgraber et al., 1998). This paper describes the integration and performance of RF transistors and passive components in a FD-SOI process which work in the L-band for portable wireless applications. In this work, we show that by using high-resistivity substrates, simple integration can be achieved. Our analysis of RF devices indicates that RF noise figure (NF) and linearity (IP3) are critical parameters affected by the substrate, the Q-factor of passive elements, and “kink” in the transistor I <sub>d</sub>-V<sub>ds</sub> characteristic
SOI Conference, 2000 IEEE International; 02/2000
-
[show abstract]
[hide abstract]
ABSTRACT: Short-channel effects (SCE) in ultrathin silicon-on-insulator
(SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model
for threshold voltage, including the kink effect, is presented. The
proposed model accounts for (1) a general nonuniform channel doping
profile, (2) the drain-induced V<sub>th</sub>- lowering enhancement
resulting from the interaction of (a) impact ionization, (b)
floating-body, and (c) parasitic-bipolar effects. Good agreement between
the proposed model and experimental data is demonstrated. Impact
ionization and floating-body effects dominate V<sub>th</sub> lowering
for drain voltages larger than
V<sub>dk</sub>≃B<sub>i</sub>.λ<sub>i</sub>/3, where B<sub>i
</sub> is the impact ionization coefficient, and λ<sub>i</sub> is
the impact ionization length, a structural parameter which, for a
single-drain SOI MOSFET, coincides with the SCE characteristic length
λ
IEEE Transactions on Electron Devices 05/1999; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I<sub>doff</sub><10 pA/μm, which should be compared with I<sub>doff</sub>~1 nA/μm in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC's standby current for quantitative modeling. The model parameter extraction techniques are also described
SOI Conference, 1999. Proceedings. 1999 IEEE International; 02/1999
-
[show abstract]
[hide abstract]
ABSTRACT: Silicon on insulator (SOI) based devices have been a research
theme for about two decades. The advantages over bulk Si are clear and
SOI substrates have been expected to break into the mainstream CMOS IC
industry. Until now, these expectations have not been realized. The
reasons behind this include: (i) SOI wafer availability, quality and
cost; (ii) SOI MOSFET floating body effects and lower breakdown voltage;
and (iii) economic reasons that propel bulk CMOS advances in circuit
techniques and process technology. This situation is now changing.
Battery operated portable devices are called to perform advanced
functions that include communication in the RF spectrum at frequencies
in the 400 MHz to 2.5 GHz range, as well as complex signal and graphic
processing. The low voltage, low power and high performance requirements
are showing the limitations of bulk CMOS and are opening a new
opportunity for SOI. In this paper, the status of SOI device
applications and manufacturing considerations are reviewed
SOI Conference, 1998. Proceedings., 1998 IEEE International; 11/1998
-
[show abstract]
[hide abstract]
ABSTRACT: Summary form only given. SOI MOSFETs implemented on ultra-thin
superficial Si film are regarded as promising candidates for the
deep-half micron CMOS generation due to their excellent characteristics.
To assess the transistor and technology design, however, a compact
analytical model that includes the important floating body effects is
needed. In this work, a physics-based analytical model for the threshold
voltage Vth, that considers (i) a more general non-uniform channel
profile and (ii) also the floating body effects, and parasitic bipolar
action, that greatly degrade DIBL, is presented. Threshold lowering in
the saturation regime is important since it determines Ioff leakage and
standby current. These effects have not been included in previous
models, and therefore are limited in their predictions
SOI Conference, 1997. Proceedings., 1997 IEEE International; 11/1997
-
[show abstract]
[hide abstract]
ABSTRACT: A 0.35 μm CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997; 06/1997
-
[show abstract]
[hide abstract]
ABSTRACT: A 0.6 μm CMOS single-polycide, double-metal, EEPROM technology
for Programable Logic Device applications is described. A channel-stop
implantation through an optimized LOCOS, and a compensated P-well
profile at the N+/P junction, results in an aggressive 1.5 μm field
isolation pitch that satisfies the 12.5 V high-voltage requirement. The
FN tunneling currents allow on-chip high-voltage generation from a
single power supply for ISP applications. The EPM7032A and EPM7128E PLD
products propagation delay time of 4.4 nsec and 6.8 nsec respectively,
are the fastest reported at 32 and 128 macro-cell densities
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995; 06/1995
-
[show abstract]
[hide abstract]
ABSTRACT: Double-gated poly-Si MOS thin film transistors (TFTs), having two
gate electrodes (top and bottom) connected together, are analyzed by the
numerical solution of the Poisson equation. It is found that for fully
inverted films there is a strong coupling of the top and bottom
channels, resulting in a more efficient channel charge modulation and
substantial improvement of electrical characteristics: reduction of
subthreshold swing, reduction of threshold voltage, enhancement of drive
current, and suppression of punch-through degradation in submicron
channel length TFTs. By applying the double-gated structure, submicron
poly Si PMOS TFTs have been realized with 0.6 μm channel length, OFF
current of 0.4 pA/μm, and ON/OFF ratio >5×15<sup>5</sup>,
demonstrating the applicability of this device in ULSI SRAM cells
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International; 01/1991
-
[show abstract]
[hide abstract]
ABSTRACT: An SRAM cell structure using stacked double-gated, self-aligned
polysilicon PMOS thin-film transistors (TFT) is described. This memory
cell has been realized in a half-micron, triple-poly, double-metal CMOS
process; the cell area is 22.32 μm<sup>2</sup>, adequate for 4-Mb
SRAMs. The main features are: (i) self-aligned structure to precisely
define the TFT channel, (ii) TFT drive current enhancement by double
gate effect, and (iii) the realization of sub-micron channel length
TFTs, which demonstrates the feasibility of this cell for the
next-generation 16-Mb SRAM
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on; 07/1990
-
[show abstract]
[hide abstract]
ABSTRACT: Summary form only given. SOI based devices bring the potential of
very low voltage operation at high speed as required in portable
electronic systems. However, to realize the advantages of SOI MOSFETs in
a commercial product (1) high-performance transistors, with (2)
reproducible and good controllability need to be realized. Furthermore,
(3) reliability against the environment (e.g. ESD) must be demonstrated.
In this work, a high performance 0.35 μm CMOS process implemented on
ultra-thin (shallow) SIMOX wafers is presented. This process is aimed at
low-power, low-voltage (Vdd=l to 1.8 V) and high speed application for
portable communication devices. The main considerations in the
process/device design and integration are discussed and
manufacturability demonstrated
SOI Conference, 1996. Proceedings., 1996 IEEE International;
-
[show abstract]
[hide abstract]
ABSTRACT: Fully depleted (FD) MOSFETs on SOI substrate have the potential performance required for low-voltage, high-speed applications; however controllability and low drain-source breakdown (BVdss) have been pointed out. In this work, a new transistor channel-drain lateral profile engineering approach is presented and its potential to reduce the short-channel degradation and the parasitic bipolar effect on Vth roll-off and BVdss is experimentally demonstrated in a 0.35-μm CMOS on SIMOX process
SOI Conference, 1996. Proceedings., 1996 IEEE International;
