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Churoo Park,
HoeJu Chung,
Yun-Sang Lee,
Jae-Kwan Kim,
Jae-Jun Lee,
Moo-Sung Chae,
Dae-Hee Jung,
Sung-Ho Choi,
Seung-young Seo,
Taek-Seon Park,
Jun-Ho Shin,
Jin-Hyung Cho,
Seunghoon Lee,
Kyu-hyoun Kim,
Jung-Bae Lee, Changhyun Kim,
Soo-In Cho
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ABSTRACT: A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in 80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD protection, rendering C<sub>10</sub> minimization for the enhanced signal integrity in point-to-2points interfacing. Hybrid latency control scheme is proposed to achieve higher bandwidth as well as to efficiently turn DLL on and off. Temperature readout and per-bank-refresh is also implemented.
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-μm, 2-metal layers DRAM process, and the active area is 330 × 66 μm<sup>2</sup>. It exhibits 200 mV × 690 ps eye windows on the given channel with a 1.8-V supply voltage.
IEEE Journal of Solid-State Circuits 02/2005; · 3.23 Impact Factor
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ABSTRACT: This paper proposes a 128-Mb multimedia-specific DRAM having 4 independent 4Gbps serial ports, 16 independent banks, and 512b I/O bus. The core bandwidth of 51.2-Gbps is fully utilized by the four independent RX-TX 4-Gbps serial ports. The over-sampling clock/data recovery, boosted column select, and data-line redundancy schemes realize high-speed data path. It is fabricated using 1.8V, 0.10μm standard DRAM technology.
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 μm DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the charge pump, is proposed. It makes the output of the charge pump virtually grounded, to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a speed of 1.4 Gb/s.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10μm DRAM CMOS process in 330x66μm<sup>2</sup>. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: With a robust array power supply, the array noise is remarkably suppressed in 256-Mb packet-based DRAM. The array power supply is equipped with direct driver discharge, Vgs clamp, high-VCC compensator, and low-VCC Vgs booster. The VCCA drop and overshoot are improved from 133 mV to 70 mV and from 260 mV to 120 mV, respectively, as all these features are included. The tranquil VCCA results in active restoration improvement by 3.0 ns in the full chip performance. The suppression of the VCCA overshoot makes high speed operation reliable owing to rapid column precharge. The power consumption by the VCCA generator is also reduced by 35% because of the time-variant DC current control.
VLSI Circuits Digest of Technical Papers, 2002. Symposium on; 02/2002
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ABSTRACT: A high-speed I/O circuit for the memory interface is implemented in a 0.25µm CMOS technology. To increase the sensitivity of the input circuit, the receiver employs the positive feedback. For driving of signal with the proper slew rate and specified voltage level under PVT variations, the pro-posed output circuit includes the novel level detection circuit and slew rate control scheme.
Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European; 10/2001
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ABSTRACT: A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ
organization architecture achieving a peak bandwidth of 2.0-GB/s at V
<sub>DD</sub>=2.25 V and T=100°C has been developed using (1) an
area- and performance-efficient chip architecture with a mixture of
high-speed interface circuits with DRAM peripheral circuits to increase
cell efficiency; (2) a multilevel controlled bitline equalizing scheme
and a distributed sense amplifier driving scheme to enhance DRAM core
timing margin while increasing the number of cells per wordline for cell
efficiency over the previous subwordline driving scheme; (3) a flexible
column redundancy scheme with multiple fuse boxes instead of excessive
spare memory cell arrays for 143 internal I/O architecture; and (4)
optimized I/O circuits and pin parasitic design including pad and
package to maximize the operating frequency
IEEE Journal of Solid-State Circuits 06/2001; · 3.23 Impact Factor
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ABSTRACT: This paper describes a dual-loop delay-locked loop (DLL) which
overcomes the problem of a limited delay range by using multiple
voltage-controlled delay lines (VCDLs). A reference loop generates
quadrature clocks, which are then delayed with controllable amounts by
four VCDLs and multiplexed to generate the output clock in a main loop.
This architecture enables the DLL to emulate the infinite-length VCDL
with multiple finite-length VCDLs. The DLL incorporates a replica
biasing circuit for low-jitter characteristics and a duty cycle
corrector immune to prevalent process mismatches. A test chip has been
fabricated using a 0.25-μm CMOS process. At 400 MHz, the peak-to-peak
jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise
sensitivity is 0.32 ps/mV
IEEE Journal of Solid-State Circuits 06/2001; · 3.23 Impact Factor
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ABSTRACT: A prototype 1 Gbit synchronous DRAM with independent
subarray-controlled isolation and hierarchical decoding schemes is
demonstrated to alleviate the difficulties encountered in high-density
devices with regard to failure analysis and performance optimization.
The scheme to isolate memory arrays from “hard” defects and
to overcome the dc leakages of “soft” defects with external
sources allows monitoring of the leakage current for the defect analysis
and testing of the device without being limited by the capabilities of
on-chip voltage sources. A hierarchical decoding scheme with a dynamic
CMOS series logic predecoder achieves improvements in circuit speed,
power, and complexity. As a result, evaluation of the prototype devices
can be facilitated, and the optimized circuit schemes achieve enhanced
circuit performance. A fully working 1 Gbit synchronous DRAM with a chip
size of 570 mm<sup>2</sup> was fabricated using a 0.16 μm CMOS
process and tested for excellent functionality up to 143 MHz
IEEE Journal of Solid-State Circuits 06/1998; · 3.23 Impact Factor
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Kyuchan Lee, Changhyun Kim,
Dong-Ryul Ryu,
Jai-Hoon Sim,
Sang-Bo Lee,
Byung-Sik Moon,
Keum-Yong Kim,
Nam-Jong Kim,
Seung-Moon Yoo,
Hongil Yoon,
Jei-Hwan Yoo,
Soo-In Cho
[show abstract]
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ABSTRACT: This paper describes several new circuit design techniques for low
V<sub>CC</sub> regions: 1) a charge-amplifying boosted sensing (CABS)
scheme which amplifies the sensing voltage difference (ΔV<sub>BL
</sub>) as well as the V<sub>GS</sub> margin by boosting the sensing
node voltage with a voltage dependent boosting capacitor and 2) an I/O
current sense amplifier with a high gain using a cross-coupled current
mirror control scheme and reduced temperature sensitivity using a simple
temperature-compensation scheme. An experimental 16 Mb DRAM chip with
the 0.18-μm twin-well, triple-metal CMOS process has been fabricated,
and an access time from the row address strobe (t<sub>RAC</sub>) of 28
ns at V<sub>cc</sub>=1.5 V and T=25°C has been obtained
IEEE Journal of Solid-State Circuits 06/1997; · 3.23 Impact Factor
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Daeje Chin, Changhyun Kim,
Yunho Choi,
Dong-Sun Min,
Hong-Sun Hwang,
Hoon Choi,
Sooin Cho,
Tae Young Chung,
Chan J. Park,
Yunseung Shin,
Kwangpyuk Suh,
Yong E. Park
IEEE Journal of Solid-State Circuits 11/1989; 24(5):1191- 1197. · 3.23 Impact Factor
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Daeje Chin, Changhyun Kim,
Y.H. Choi,
D.S. Min,
H.S. Hwang,
Hoont Choi,
S.I. Cho,
T.Y. Chung,
C.J. Park,
Y.S. Shin,
Kwangpyuk Suh,
Y.E. Park
VLSI Circuits, 1989. Digest of Technical Papers., 1989 Symposium on; 02/1989
