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ABSTRACT: Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 μs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.
IC Design and Technology (ICICDT), 2010 IEEE International Conference on; 07/2010
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ABSTRACT: A MIMO 3GPP-LTE digital baseband chip based on a heterogeneous 3 à 5 array NoC using 3.2 GOPS/50 mW programmable VLIW cores is presented. It features less than 10 ¿s run-time full physical layer reconfiguration and distributed power management leading to 477 mW power consumption on a 4 à 2 MIMO RX application.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
