H.F. Luan

Publications (23)13.39 Total impact

• Article: Metal gate work function engineering using AlNx interfacial layers

  H. N. Alshareef, H. F. Luan, K. Choi, H. R. Harris, H. C. Wen, M. A. Quevedo-Lopez, P. Majhi, B. H. Lee
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  ABSTRACT: Metal gate work function enhancement using thin Al N _x interfacial layers has been evaluated. It was found that band edge effective work functions (∼5.10 eV ) can be achieved on hafnium-based high dielectric constant (high- k ) materials using the Al N _x interfacial layer and TiSiN electrodes. It was also found that the effective work function enhancement by the Al N _x interfacial layer increased when the concentration of Si O ₂ in the gate dielectric was increased. Thus, the enhancement was minimal for Hf O ₂ and maximum for Si O ₂ . A model is proposed to explain these results and a bonding analysis is presented to support the proposed model.
  Applied Physics Letters 04/2006; · 3.84 Impact Factor
• Article: Modulation of the work function of silicon gate electrode using thin TaN interlayers

  H. N. Alshareef, H. C. Wen, H. R. Harris, K. Choi, H. F. Luan, P. Lysaght, P. Majhi, B. H. Lee, M. El-Bouanani, V. Ukride
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  ABSTRACT: The impact of thin TaN layers (0.5–10 nm) on the effective work function of polycrystalline silicon (poly-Si)∕TaN stacks has been investigated. It is found that when the TaN layer is as thin as 0.5 nm, it can have a significant effect on the effective work function of poly-Si, and that n-type and p-type poly-Si behave differently. The observed results are explained by reactions between poly-Si and the TaN layer leading to the formation of TaxSiyNz at the poly-Si-gate dielectric interface. Electrical tests show minimal poly-Si depletion with the TaN layers, and gate leakage current and fixed charges that are comparable to conventional poly-Si electrodes. The results show that these stacked electrodes can be useful for nearly n-type effective work functions (4.2–4.3 eV).
  Applied Physics Letters 07/2005; 87(5):052109-052109-3. · 3.84 Impact Factor
• Source

  Available from: berkeley.edu

  Article: Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric

  Qiang Lu, Yee Chia Yeo, K.J. Yang, R. Lin, I. Polishchuk, Tsu-Jae King, Chenming Hu, S.C. Song, H.F. Luan, Dim-Lee Kwong, Xin Guo, Zhijiong Luo, Xiewen Wang, Tso-Ping Ma
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  ABSTRACT: P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.
  IEEE Electron Device Letters 08/2001; · 2.85 Impact Factor
• Source

  Available from: berkeley.edu

  Article: Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

  Yee-Chia Yeo, Qiang Lu, P. Ranade, H. Takeuchi, K.J. Yang, I. Polishchuk, Tsu-Jae King, Chenming Hu, S.C. Song, H.F. Luan, Dim-Lee Kwong
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  ABSTRACT: We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.
  IEEE Electron Device Letters 06/2001; · 2.85 Impact Factor
• Conference Proceeding: High-k gate dielectrics for sub-100 nm CMOS technology

  S.J. Lee, C.H. Lee, Y.H. Kim, H.F. Luan, W.P. Bai, T.S. Jeon, D.L. Kwong
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  ABSTRACT: In this paper, the materials and processing challenges for the fabrication of high-quality. ultra-thin (EOT<1 run) high-K gate stack for sub-100 nm CMOS technology are reviewed along with our recent results on CVD HfO₂. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest EOT are discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and high-K/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in the high-K gate stack. Both poly-Si and metal nitrides are explored as possible gate electrode materials arid the upper thermal budget limit for such materials are discussed
  Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on; 02/2001
• Conference Proceeding: Performance and reliability of ultra thin CVD HfO2 gate dielectrics with dual poly-Si gate electrodes

  S.J. Lee, H.F. Luan, C.H. Lee, T.S. Jeon, W.P. Bai, Y. Senzaki, D. Roberts, D.L. Kwong
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  ABSTRACT: MOSFETs with high quality ultra thin (EOT~10.3 Å) HfO₂ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO₂ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050°C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing
  VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on; 02/2001
• Conference Proceeding: Dual-poly CVD HfO2 gate stack for sub-100 nm CMOS technology

  S.J. Lee, C.H. Lee, Y.H. Kim, H.F. Luan, W.P. Bai, T.S. Jeon, D.L. Kwong
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  ABSTRACT: In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO₂. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed
  Gate Insulator, 2001. IWGI 2001. Extended Abstracts of International Workshop on; 02/2001
• Conference Proceeding: MOS devices with high quality ultra thin CVD ZrO2 gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

  C.H. Lee, Y.H. Kim, H.F. Luan, S.J. Lee, T.S. Jeon, W.P. Bai, D.L. Kwong
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  ABSTRACT: In this paper, we have successfully fabricated and characterized self-aligned TaN and TaN/poly-Si gated n-MOSFETs with ultra thin (EOT=11 Å) CVD ZrO₂ gate dielectrics. It is show that while both gate stacks show excellent leakage current and good thermal stability after a 900°C, 30 s, N₂ anneal, the TaN/poly-Si ZrO₂ devices exhibit superior thermal stability even after 1000°C, 30 s, N₂ anneal. In addition, the TaN/poly-Si devices show negligible frequency dependence of CV, charge trapping, and superior TDDB characteristics, compared to TaN devices. Well-behaved N-MOSFETs with both TaN and TaN/poly-Si gate electrodes are demonstrated
  VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on; 02/2001
• Source

  Available from: berkeley.edu

  Conference Proceeding: Dual-metal gate technology for deep-submicron CMOS transistors

  Qiang Lu, Yee Chia Yeo, P. Ranade, H. Takeuchi, Tsu-Jae King, Chenming Hu, S.C. Song, H.F. Luan, Dim-Lee Kwong
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  ABSTRACT: Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si₃N₄ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO₂. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates
  VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
• Conference Proceeding: High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode

  S.J. Lee, H.F. Luan, W.P. Bai, C.H. Lee, T.S. Jeon, Y. Senzaki, D. Roberts, D.L. Kwong
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  ABSTRACT: We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO ₂ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO₂ gate stack show excellent interface properties, EOT=10.4 Å, and leakage current Jg=0.23 mA/cm² @Vg=-1 V which is several orders of magnitude lower than RTO SiO₂ with poly-Si gate. In addition, the HfO₂ gate stack is thermally stable in direct contact with n⁺-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO₂ gate stack with p⁺-poly Si gate
  Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
• Conference Proceeding: MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics

  C.H. Lee, H.F. Luan, W.P. Bai, S.J. Lee, T.S. Jeon, Y. Senzaki, D. Roberts, D.L. Kwong
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  ABSTRACT: In this paper, we report MOS characteristics of ultra thin, high quality CVD ZrO₂ and Zr silicate (Zr₂₇Si₁₀O₆₃) gate dielectrics deposited on Si substrates by in-situ rapid thermal processing. These high-K gate dielectrics show excellent equivalent oxide thickness (EOT) of 8.9 Å (ZrO₂) and 9.6 Å (Zr₂₇Si₁₀O₆₃) with extremely low leakage current of 20 mA/cm² and 23 mA/cm ² @Vg=-1 V, respectively. The thermal stability of ZrO₂/Si as well as the poly-Si/ZrO₂ interfaces are examined using in-situ XPS. We also investigate the conduction mechanisms and long-term reliability in these gate stacks. In addition, the effects of various gate electrode materials (Al/TiN, poly-SiGe, and poly-Si) on the electrical properties of gate stacks are studied. Finally, we also study the boron diffusion behaviors in p⁺-poly-Si PMOS
  Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
• Conference Proceeding: Ultra thin high quality stack nitride/oxide gate dielectricsprepared by in-situ rapid thermal N₂O oxidation of NH₃-nitrided Si

  S.C. Song, H.F. Luan, C H Lee, A.Y. Mao, S J Lee, J. Gelpey, M. Marcus, D.L. Kwong
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  ABSTRACT: In this paper, we report ultra thin high quality nitride/oxide gate dielectrics prepared by rapid thermal NH₃ nitridation of Si followed by in-situ N₂O oxidation (NH₃+N₂O process). These films show excellent interface properties, significant lower leakage current (~10²×), enhanced reliability, and superior boron diffusion barrier properties compared with SiO₂ of identical thickness
  VLSI Technology, Systems, and Applications, 1999. International Symposium on; 02/1999
• Conference Proceeding: High quality Ta2O5 gate dielectrics with T ox.eq<10 Å

  H.F. Luan, S.J. Lee, C.H. Lee, S.C. Song, Y.L. Mao, Y. Senzaki, D. Roberts, D.L. Kwong
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  ABSTRACT: High quality Ta₂O₅ gate stack with T_ox,eq=9 Å (measured @ Vg=-2.5 V in strong accumulation without taking quantum mechanical effects into account) and the leakage current Jg=0.19 A/cm² @ Vg=-1.0 V has been achieved using NH ₃-based interface layer, H₂/O₂ post-deposition anneal and TiN diffusion barrier. The leakage current of Ta₂O₅ gate stack with NO interface layer is 10⁴x lower than that of RTP SiO₂ with same T_ox,eq and can be further reduced by a factor of 100 with NH ₃-based interface layer
  Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
• Conference Proceeding: A manufacturable multiple gate oxynitride thickness technology for system on a chip

  C.H. Lee, H.F. Luan, S.C. Song, S.J. Lee, B. Evans, D.L. Kwong
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  ABSTRACT: System-on-a-chip has received considerable attention for future CMOS technology. One of the major technological requirements of system-on-a-chip is the ability to grow multiple gate oxide thickness simultaneously on a wafer with significantly differential oxide growth rate. System-on-a-chip has become the trend of future CMOS technologies. Combining logic circuits and several different memory elements in one chip with multiple supply voltages requires the use of multiple gate oxides or oxynitride thicknesses on the same wafer. In this paper, a novel approach to realize >500% difference in oxide growth rate is demonstrated for the first time using Vertical High Pressure (VHP) oxidation (15-25 atm @ 750-800°C) and N implantation (1E14-3E15 atoms/cm²)
  Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
• Conference Proceeding: Ultra thin high quality stack nitride/oxide gate dielectricsprepared by in-situ rapid thermal N₂O oxidation of NH₃-nitrided Si

  S.C. Song, H.F. Luan, C H Lee, A.Y. Mao, S J Lee, J. Gelpey, S. Marcus, D.L. Kwong
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  ABSTRACT: In this paper, we report ultra thin high quality nitride/oxide gate dielectrics prepared by rapid thermal NH₃ nitridation of Si followed by in-situ N₂O oxidation (NH₃+N₂O process). These films show excellent interface properties, significantly lower leakage current (~10²×), enhanced reliability, and superior boron diffusion barrier properties compared with SiO₂ of identical thickness
  VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
• Conference Proceeding: Ultra thin high quality Ta2O5 gate dielectric prepared by in-situ rapid thermal processing

  H.F. Luan, B.Z. Wu, L.G. Kang, B.Y. Kim, R. Vrtis, D. Roberts, D.L. Kwong
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  ABSTRACT: In this paper, ultra thin CVD Ta₂O₅ gate dielectrics (Teq<15 Å) with significantly lower leakage current compared to SiO₂, of identical thickness, have been fabricated by in-situ RTP processing. Superior interface properties and reliability have been obtained
  Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999
• Conference Proceeding: Ultra thin (<20 Å) CVD Si3N4 gate dielectric for deep-sub-micron CMOS devices

  S.C. Song, H.F. Luan, Y.Y. Chen, M. Gardner, J. Fulford, M. Allen, D.L. Kwong
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  ABSTRACT: In this paper, we report the first sub-micron n- and p-MOSFETs with ultra thin (<20 Å) Si₃N₄ gate dielectric fabricated by in-situ rapid thermal CVD (RTCVD) process, and compare their performance and reliability with control SiO₂ devices of identical equivalent oxide thickness (T_eq). Both n- and p-MOSFETs with CVD Si₃N₄ gate dielectric show higher drain current and peak transconductance, enhanced immunity to hot carrier stress, and significant reduction of tunneling leakage current
  Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999
• Conference Proceeding: MOSFET characteristics of ultra thin CVD Si3N4 gate dielectrics

  S.C. Song, H.F. Luan, Y Y Chen, D.L. Kwong, M. Gardener, J. Fulford, M. Allen
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  ABSTRACT: Not Available
  Solid-State Device Research Conference, 1998. Proceeding of the 28th European; 10/1998
• Source

  Available from: stanford.edu

  Conference Proceeding: Ultra thin (<3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing

  B.Y. Kim, H.F. Luan, D.L. Kwong
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  ABSTRACT: In this paper, ultra thin (<3 nm) Si₃N₄/SiO₂ stack layer with significant lower leakage current, superior boron diffusion barrier properties, and reliability compared with SiO₂ of identical thickness have been fabricated by in-situ RTP processing. These results demonstrate for the first time that ultra thin LPCVD Si₃N₄ can be used as gate dielectrics, contrary to those conclusions made previously on thicker LPCVD Si₃N₄
  Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998
• Conference Proceeding: Impact of boron penetration on gate oxide reliability and devicelifetime in p⁺-poly PMOSFETs

  B.Y. Kim, I.M. Liu, H.F. Luan, M. Gardner, J. Fulford, D.L. Kwong
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  ABSTRACT: The effect of boron penetration on device performance and reliability of p⁺-poly PMOSFETs was investigated in a wide RTA drive-in temperature range. High RTA drive-in temperature reduces the poly-depletion effect in NMOSFETs while causing significant boron-penetration induced mobility degradation in PMOSFETs, leading to difficulty in I_d,sat optimization for a dual-gate CMOS process. Moreover, boron penetration enhances charge trapping in the oxide and interface state generation at the Si-SiO₂ interface under F-N stress. The impact of this degradation mode on gate oxide reliability and device lifetime in the PMOSFETs is systematically demonstrated
  Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International; 05/1997