G. Passemard

STMicroelectronics, Genève, Geneva, Switzerland

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Publications (90)51.04 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: To meet requirements of CMOS circuits at sub 45nm scale, gate oxide thickness shall decrease. Thus high K materials are needed as dielectric gate. In this setting, due to gate depletion effect, metallic material should be used as an alternative to poly silicon gate. Moreover, specifications on threshold voltage require modulation of gate material work function with respect to nMOS or pMOS transistor. WSi x work function is known to be sensitive to material stoichiometry. In this work, WSi x thin films with x between 2.2 and 2.5 are evaluated as metal gate on HfO 2 and SiO 2 dielectric. Film chemical characteristics are correlated with work function measurements. Thin films are deposited using WF 6 and dichlorosilane on a 200mm wafer industrial chamber. Thermal treatments are applied to sample in order to recrystallise the film and confirm it stability. MOS Capacitors are processed. Electrical characterizations (capacitance vs voltage) are used to extract work function with respect to film composition. Films are chemically and morphologically stable up to 800°C. A W/Si ratio gradient is observed between surface and dielectric/film interface. Whatever the nominal stoichiometry, Si/W ratio is constant at this interface. This result is correlated with identical work function measurement for different nominal stoichiometry. Moreover no differences are observed between Vfb vs equivalent oxide thickness curves for HfO 2 and SiO 2 dielectric. High EOT variations have been identified for SiO 2 capacitors in contrast with SiO 2/HfO 2 capacitors. These results characterize WSi x as a suitable metal gate for nMOS transistors.
    MRS Online Proceeding Library 01/2011; 786. DOI:10.1557/PROC-786-E6.32
  • Sylvain Maitrejean · Roland Gers · Thierry Mourier · Alain Toffoli · Gérard Passemard ·
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    ABSTRACT: As the dimensions of interconnects shrink, the confinement effects associated with a very small grain size lead to a significant increase in the resistivity of the metal. Cu resistivity models have been proposed using the classical Fuch and Sondheimer approach for surface effect, and the Mayadas and Shatzkes approach for the grain boundary effect. In these models, three adjustable parameters must be used. Good agreement between experimental data and models can easily be obtained. However, numerous fitting parameter sets can be used with equivalent fitting quality and opposite physical meaning. In this work, experiments dedicated to model parameter extraction are proposed and released. They are based on the used of Cu lines with various line widths and heights. Classical resistivity increase with line width and line height decrease is observed. The resistivity behaviour is modelled. In this case, limited fitting parameter options are obtained. For Cu narrow lines confined with Ta, these parameters suggest maximum surface effect, medium grain boundary effect and low impurity content inside the lines.
    MRS Online Proceeding Library 01/2011; 914. DOI:10.1557/PROC-0914-F09-07

  • MRS Online Proceeding Library 01/2011; 914. DOI:10.1557/PROC-0914-F02-08
  • Stéphane Moreau · Sylvain Maitrejean · Gérard Passemard ·
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    ABSTRACT: Fatigue in damascene copper line has been investigated by using alternating currents to generate cyclic temperatures and stresses/strains. Interconnects using beyond 65 nm node design rules and materials have been studied. We demonstrate that cyclic thermal strains lead to Cu or Cu/Co-based cap surface modification and open circuits in Cu lines during the application of an alternating electrical current. We underline that the narrower the copper lines are, the more reliable they are and the major role of the cap layer to improve the Cu lines reliability. Moreover, a statistical approach is presented in this paper in order to discuss about the thermal fatigue associated distribution model (exponential, lognormal and Weibull distributions). At present, the lognormal distribution seems to be the most appropriate one.
    MRS Online Proceeding Library 01/2011; 990. DOI:10.1557/PROC-0990-B07-17
  • M. Verdier · M. Montagnat · S. Maîtrejean · G. Passemard ·

    MRS Online Proceeding Library 01/2011; 795. DOI:10.1557/PROC-795-U5.26
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    ABSTRACT: The use of porous ultra-low-k materials between interconnections for sub 45nm technologies has introduced some barrier diffusion and mechanical problems. In order to avoid the problems caused by the porosity, a hybrid dense material (porogen and matrix) can be used in an alternate integration scheme. In this approach, the porogen is removed after CMP steps by a thermal cure or UV assisted thermal cure. In this work, we have first characterized the impact of the temperature and the duration of the thermal cure on the material. The crosslinking degree increases and the porogen amount decreases with increasing cure temperature. The most important impact of the curing duration happens between 350°C and 400°C. The increase of the curing duration leads to an increase of the porogen loss and a decrease of the refractive index. Secondly, in order to assess the structure of the layer as a function of the depth, the material was etched in a 0.05% HF solution and then characterized. According to the temperature and duration of the cure, the etch-rate can vary as a function of the material depth. This variation is related to a complex gradient inside the material.
    MRS Online Proceeding Library 01/2011; 914. DOI:10.1557/PROC-0914-F02-04
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    ABSTRACT: We describe progress in understanding the effect of simulated chemical-mechanical planarization (CMP) slurry chemistry on the evolution of defects and formation of damage that occurs during CMP processing. Specifically, we demonstrate the significant effect of aqueous solution chemistry on accelerating crack growth in porous methylsilsesquioxane (MSSQ) films. In addition, we show that the same aqueous solutions can diffuse rapidly into the highly hydrophobic nanoporous MSSQ films containing interconnected porosity. Such diffusion has deleterious effects on both dielectric properties and the acceleration of defect growth rates. Crack propagation rates were measured in several CMP solutions, and the resulting crack growth behavior was used to qualitatively predict the extent of damage during CMP. These predictions are compared with damage formed during actual CMP processes in identical chemistries. We discuss the effects of both the high and low crack growth rate regimes, including the presence of a crack growth threshold, on the predicted CMP damage. Finally, implications for improved CMP processing were considered.
    09/2010; 25(10):1904 - 1909. DOI:10.1557/JMR.2010.0249
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    ABSTRACT: We investigate the nucleation and growth of two cobalt alloys (CoWB and Pd-CoWP) used to encapsulate copper interconnects. We demonstrate that very uniform deposits are obtained across 300mm wafers, with accurate thickness control. However, large local thickness variations are observed, possibly compromising the continuity of thin deposits. The origin of this phenomenon is first investigated by electron back scatter diffraction. A clear correlation between areas of dense Pd nucleation and the (111) grains of the polycrystalline copper surface is demonstrated. Then, an epitaxial relationship between the cobalt alloys and the underlying copper substrate is evidenced by TEM characterization. Local nucleation density could thus be affected by the substrate orientation, accounting for thickness inhomogeneities after growth.
    Thin Solid Films 06/2010; 518(17):4773-4778. DOI:10.1016/j.tsf.2010.01.025 · 1.76 Impact Factor
  • S. MoreaUaa · J.-C. Barbea · P. Leduc · S. Maitrejean · G. Passemard ·
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    ABSTRACT: The Chemical-Mechanical Polishing (CMP) process is still challenging for the semiconductor industry: during this key step, decohesion/adhesion fracture often occurs. The authors have developed a specific methodology in order to estimate this potential risk. This methodology uses finite element simulations in conjunction with a post-treatment computing the Energy Release Rate (ERR) which is related to the risk of delamination To perform the ERR calculation, the Virtual Crack Closure Technique (VCCT) was implemented. This methodology was used for ULK/Cu integration and was validated through experiments. The impact of the process on the wafer residual stress was exhibit. From the fracture point of view, the authors confirm the delamination increases with ULK levels and with lower dielectric elastic modulus.
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    V. Carreau · S. Maitrejean · Y. Brechet · M. Verdier · D. Bouchu · G. Passemard ·
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    ABSTRACT: With the reduction of dimensions in interconnect copper lines, metal resistivity is seen to increase. This phenomenon is due to electron scattering on both sidewalls and grain boundaries. To reduce the grain boundary contribution and then resistivity, it becomes important to control microstructure. This paper focuses on the grain growth mechanism in a Damascene architecture. In this architecture, trenches are filled with copper. It is shown that the remaining copper on the top surface – the overburden – plays a key role in the final microstructure in the lines. Electrical results and observations are presented and discussed in terms of overburden grains extension inside the trenches. A method is proposed to quantify this grain extension.
    Microelectronic Engineering 10/2008; 85(10):2133-2136. DOI:10.1016/j.mee.2008.04.049 · 1.20 Impact Factor
  • Ségolène Olivier · Tifenn Decorps · M. Bernard · P.H. Haumesser · Gérard Passemard ·
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    ABSTRACT: With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm2, copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.
    Microelectronic Engineering 10/2008; 85(10-85):2051-2054. DOI:10.1016/j.mee.2008.04.015 · 1.20 Impact Factor
  • A. Castex · V. Jousseaume · J. Deval · J. Bruat · L. Favennec · G. Passemard ·
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    ABSTRACT: As interconnects are scaled down, much effort is made to achieve ultralow k material with a dielectric constant lower than 2.5. Thus, many new precursors are investigated in plasma-enhanced chemical vapor deposition. This is particularly true with the porogen approach where two molecules are used: an organosilicon to create the silicon matrix and an organic molecule 'porogen' that creates material porosity during a post-treatment such as annealing. In this article, the influence of the organosilicon molecular structure is investigated. Two 'matrix precursors' with different structures are therefore compared. The first one, referred to as D5, has a ring structure (decamethyl pentacyclosiloxane); the second one, referred to as DEOMS, has a star structure (diethoxymethyl silane). The porogen organic molecule, referred to as CHO, is cyclohexen oxide. The fragmentation paths of the precursor molecules in the plasma are investigated by quadrupole mass spectroscopy and the film structure is studied by Fourier transform infrared spectroscopy. The mass spectroscopy analysis shows that the fragmentation in plasma is highest for DEOMS, intermediate for CHO, and lowest for D5 in comparable process conditions. At the maximum plasma power setting, the loss rate, which yields molecule consumption, is 43%-81% for the D5-CHO mixture, respectively, and 73%-37% for the DEOMS-CHO mixture, respectively. This is related to higher bond-dissociation energy for the siloxane (Si-O-Si) link in D5 than silane (Si-H), silylethoxyde (Si-OCH) in DEOMS, or C-C and epoxy cycle in CHO. Indeed, a higher electron-energy relative threshold for dissociation under electron impact is measured for D5 (around 7 eV) than for DEOMS and CHO (around 4 eV). Moreover, the fragment structures differ from one precursor to another. Methyl groups are abstracted from D5 and a few polysiloxane chains are produced from pentacycle opening and fragmentation. In the case of DEOMS, many single silicon-atom-bearing species are produced. Consequently, the D5-based films have significant retention of siloxane cycles and a less diverse silicon environment than DEOMS-based films. The porogen incoporation (organic phase) was evidenced through alkyl group absorption and is more important with DEOMS than D5 as a matrix precursor. Moreover, the epoxy moiety of the porogen seems scavenged by the plasma and is not retained in the films. These results confirm other studies that discarded D5-CHO chemistry for porous dielectric achievement in an industrial reactor, whereas DEOMS-CHO leads to porous films with an ultralow dielectric constant. Eventually, this study shows that the usefulness of cyclosiloxane precursors is not straightforward.
    09/2008; 26(5):1343-1354. DOI:10.1116/1.2953704
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    ABSTRACT: Air gaps were successfully integrated in a multi level metallization interconnect stack using 65 nm design rules on 300 mm wafers. The proposed approach allows a low cost integration of localized air cavities using a sacrificial material to solve via misalignment issues. Air gap integration is shown to be mechanically robust and presents excellent electrical results with high gains on RC delays. In addition, air gaps structures tested in electromigration pass the targeted lifetime criterion. This easily scalable approach can be seriously considered either in aggressive interconnect geometries or in specific applications of existing technologies for which high electrical performance is locally required.
    Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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    ABSTRACT: To reduce the capacitance and mimprove the reliability of metal interconnects at the 32 nm node and beyond, a promising approach is to use a direct CMP process stopping in the porous ultra-low k material combined with a metallicself-aligned CoWP capping layer. We demonstrate on 45 nm technology node wafers, that our self-aligned barrier layer process is compatible with the direct CMP process.
    Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
  • C. Ventosa · D. Rébiscoul · V. Perrut · V. Ivanova · O. Renault · G. Passemard ·
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    ABSTRACT: In this study we report the efficiency of cleaning process in supercritical CO2 for the removal of the post-etch residues and oxidized copper formed in the via after SiOC-based porous materials etching and photoresist plasma ashing processes. The cleaning solutions contain a sulfonic acid and chelating agents with different chemical configurations. X-ray reflectometry and scanning electron microscopy are used to estimate the oxidized copper dissolution and copper surface aspect (pitting corrosion and residues). The results show that the sulfonic acid dissolves cuprous oxide (Cu2O) and copper hydroxide (Cu(OH)2) and consequently allows to remove the residues located at the oxidized copper surface whereas the symmetric β-diketones remove only the copper hydroxide. The mixture of sulfonic acid and β-diketone does not lead to pits at the copper surface. This phenomenon could be due to a complex formation between copper and β-diketones facilitating the oxidized copper dissolution by the acid or could be due to copper surface protection by the adsorbed β-diketones.
    Microelectronic Engineering 07/2008; 85(7):1629-1638. DOI:10.1016/j.mee.2008.03.018 · 1.20 Impact Factor
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    ABSTRACT: In recent years, the continuous progression of ultra-large scale integration has driven the emergence of technological solutions. In particular, major challenges have been faced for the fabrication of interconnect structures, where ultra low dielectric constants are required to decrease the parasitic capacitances between metal lines. Porous material, obtained using the porogen approach, is the main candidate investigated. The curing process is critical for achieving a good control of final film structure. The integration of such material requires a good chemical and mechanical stability, particularly to maintain the structure integrity during the stressing steps: chemical mechanical polishing and packaging. In this work, Ultraviolet assisted thermal cure (or UV curing) is investigated as an alternative solution to the conventional thermal curing. Chemical and physical analyses reveal that the best porogen removal efficiency and the enhancement of matrix crosslinking are achieved when the material is UV cured. This crosslinking improvement (as indicated by higher Si–O–Si bond density in the fourier transformed infra-red spectra) can be correlated to better mechanical properties. Significantly better electrical properties (dielectric constant, leakage current and breakdown voltage) are obtained with better integrity (no moisture uptake after 1 week storage in humid atmosphere 85 °C/85% relative humidity) when the dielectric is optimally cured. Porosity evaluation reveals similar results between both curing processes with slightly larger pore size in the case of the UV cured film. Finally, a basic model is described to illustrate how the UV assisted thermal cure may improve the crosslinking in comparison to the thermal curing. Selective UV action is proposed to explain the curing process kinetics.
    Thin Solid Films 01/2008; 516(6):1097-1103. DOI:10.1016/j.tsf.2007.05.010 · 1.76 Impact Factor
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    Solid State Phenomena 01/2008; 134:321-324. DOI:10.4028/www.scientific.net/SSP.134.321

  • Solid State Phenomena 01/2008; 134:345-349. DOI:10.4028/www.scientific.net/SSP.134.345
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    Solid State Phenomena 01/2008; 134:333-336. DOI:10.4028/www.scientific.net/SSP.134.333

Publication Stats

692 Citations
51.04 Total Impact Points


  • 2007
    • STMicroelectronics
      Genève, Geneva, Switzerland
    • Université Jean Monnet
      Saint-Étienne, Rhône-Alpes, France
  • 2005
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2000-2004
    • Atomic Energy and Alternative Energies Commission
      Fontenay, Île-de-France, France
    • University of Strasbourg
      Strasburg, Alsace, France