G. Passemard

Atomic Energy and Alternative Energies Commission, Fontenay, Île-de-France, France

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Publications (71)24.08 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We describe progress in understanding the effect of simulated chemical-mechanical planarization (CMP) slurry chemistry on the evolution of defects and formation of damage that occurs during CMP processing. Specifically, we demonstrate the significant effect of aqueous solution chemistry on accelerating crack growth in porous methylsilsesquioxane (MSSQ) films. In addition, we show that the same aqueous solutions can diffuse rapidly into the highly hydrophobic nanoporous MSSQ films containing interconnected porosity. Such diffusion has deleterious effects on both dielectric properties and the acceleration of defect growth rates. Crack propagation rates were measured in several CMP solutions, and the resulting crack growth behavior was used to qualitatively predict the extent of damage during CMP. These predictions are compared with damage formed during actual CMP processes in identical chemistries. We discuss the effects of both the high and low crack growth rate regimes, including the presence of a crack growth threshold, on the predicted CMP damage. Finally, implications for improved CMP processing were considered.
    Journal of Materials Research. 09/2010; 25(10):1904 - 1909.
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    ABSTRACT: We investigate the nucleation and growth of two cobalt alloys (CoWB and Pd-CoWP) used to encapsulate copper interconnects. We demonstrate that very uniform deposits are obtained across 300mm wafers, with accurate thickness control. However, large local thickness variations are observed, possibly compromising the continuity of thin deposits. The origin of this phenomenon is first investigated by electron back scatter diffraction. A clear correlation between areas of dense Pd nucleation and the (111) grains of the polycrystalline copper surface is demonstrated. Then, an epitaxial relationship between the cobalt alloys and the underlying copper substrate is evidenced by TEM characterization. Local nucleation density could thus be affected by the substrate orientation, accounting for thickness inhomogeneities after growth.
    Thin Solid Films 01/2010; 518(17):4773-4778. · 1.87 Impact Factor
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    ABSTRACT: To reduce the capacitance and mimprove the reliability of metal interconnects at the 32 nm node and beyond, a promising approach is to use a direct CMP process stopping in the porous ultra-low k material combined with a metallicself-aligned CoWP capping layer. We demonstrate on 45 nm technology node wafers, that our self-aligned barrier layer process is compatible with the direct CMP process.
    Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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    ABSTRACT: Air gaps were successfully integrated in a multi level metallization interconnect stack using 65 nm design rules on 300 mm wafers. The proposed approach allows a low cost integration of localized air cavities using a sacrificial material to solve via misalignment issues. Air gap integration is shown to be mechanically robust and presents excellent electrical results with high gains on RC delays. In addition, air gaps structures tested in electromigration pass the targeted lifetime criterion. This easily scalable approach can be seriously considered either in aggressive interconnect geometries or in specific applications of existing technologies for which high electrical performance is locally required.
    Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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    ABSTRACT: In this study we report the efficiency of cleaning process in supercritical CO2 for the removal of the post-etch residues and oxidized copper formed in the via after SiOC-based porous materials etching and photoresist plasma ashing processes. The cleaning solutions contain a sulfonic acid and chelating agents with different chemical configurations. X-ray reflectometry and scanning electron microscopy are used to estimate the oxidized copper dissolution and copper surface aspect (pitting corrosion and residues). The results show that the sulfonic acid dissolves cuprous oxide (Cu2O) and copper hydroxide (Cu(OH)2) and consequently allows to remove the residues located at the oxidized copper surface whereas the symmetric β-diketones remove only the copper hydroxide. The mixture of sulfonic acid and β-diketone does not lead to pits at the copper surface. This phenomenon could be due to a complex formation between copper and β-diketones facilitating the oxidized copper dissolution by the acid or could be due to copper surface protection by the adsorbed β-diketones.
    Microelectronic Engineering 01/2008; 85(7):1629-1638. · 1.22 Impact Factor
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    ABSTRACT: As interconnects are scaled down, much effort is made to achieve ultralow k material with a dielectric constant lower than 2.5. Thus, many new precursors are investigated in plasma-enhanced chemical vapor deposition. This is particularly true with the porogen approach where two molecules are used: an organosilicon to create the silicon matrix and an organic molecule 'porogen' that creates material porosity during a post-treatment such as annealing. In this article, the influence of the organosilicon molecular structure is investigated. Two 'matrix precursors' with different structures are therefore compared. The first one, referred to as D5, has a ring structure (decamethyl pentacyclosiloxane); the second one, referred to as DEOMS, has a star structure (diethoxymethyl silane). The porogen organic molecule, referred to as CHO, is cyclohexen oxide. The fragmentation paths of the precursor molecules in the plasma are investigated by quadrupole mass spectroscopy and the film structure is studied by Fourier transform infrared spectroscopy. The mass spectroscopy analysis shows that the fragmentation in plasma is highest for DEOMS, intermediate for CHO, and lowest for D5 in comparable process conditions. At the maximum plasma power setting, the loss rate, which yields molecule consumption, is 43%-81% for the D5-CHO mixture, respectively, and 73%-37% for the DEOMS-CHO mixture, respectively. This is related to higher bond-dissociation energy for the siloxane (Si-O-Si) link in D5 than silane (Si-H), silylethoxyde (Si-OCH) in DEOMS, or C-C and epoxy cycle in CHO. Indeed, a higher electron-energy relative threshold for dissociation under electron impact is measured for D5 (around 7 eV) than for DEOMS and CHO (around 4 eV). Moreover, the fragment structures differ from one precursor to another. Methyl groups are abstracted from D5 and a few polysiloxane chains are produced from pentacycle opening and fragmentation. In the case of DEOMS, many single silicon-atom-bearing species are produced. Consequently, the D5-based films have significant retention of siloxane cycles and a less diverse silicon environment than DEOMS-based films. The porogen incoporation (organic phase) was evidenced through alkyl group absorption and is more important with DEOMS than D5 as a matrix precursor. Moreover, the epoxy moiety of the porogen seems scavenged by the plasma and is not retained in the films. These results confirm other studies that discarded D5-CHO chemistry for porous dielectric achievement in an industrial reactor, whereas DEOMS-CHO leads to porous films with an ultralow dielectric constant. Eventually, this study shows that the usefulness of cyclosiloxane precursors is not straightforward.
    Journal of Vacuum Science & Technology A - J VAC SCI TECHNOL A. 01/2008; 26(5):1343-1354.
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    ABSTRACT: With the reduction of dimensions in interconnect copper lines, metal resistivity is seen to increase. This phenomenon is due to electron scattering on both sidewalls and grain boundaries. To reduce the grain boundary contribution and then resistivity, it becomes important to control microstructure. This paper focuses on the grain growth mechanism in a Damascene architecture. In this architecture, trenches are filled with copper. It is shown that the remaining copper on the top surface – the overburden – plays a key role in the final microstructure in the lines. Electrical results and observations are presented and discussed in terms of overburden grains extension inside the trenches. A method is proposed to quantify this grain extension.
    Microelectronic Engineering 01/2008; 85(10):2133-2136. · 1.22 Impact Factor
  • Solid State Phenomena. 01/2008; 134:333-336.
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    ABSTRACT: The Chemical-Mechanical Polishing (CMP) process is still challenging for the semiconductor industry: during this key step, decohesion/adhesion fracture often occurs. The authors have developed a specific methodology in order to estimate this potential risk. This methodology uses finite element simulations in conjunction with a post-treatment computing the Energy Release Rate (ERR) which is related to the risk of delamination To perform the ERR calculation, the Virtual Crack Closure Technique (VCCT) was implemented. This methodology was used for ULK/Cu integration and was validated through experiments. The impact of the process on the wafer residual stress was exhibit. From the fracture point of view, the authors confirm the delamination increases with ULK levels and with lower dielectric elastic modulus.
    01/2008;
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    Solid State Phenomena. 01/2008; 134:321-324.
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    ABSTRACT: With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm2, copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.
    Microelectronic Engineering. 01/2008;
  • Solid State Phenomena. 01/2008; 134:345-349.
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    ABSTRACT: In recent years, the continuous progression of ultra-large scale integration has driven the emergence of technological solutions. In particular, major challenges have been faced for the fabrication of interconnect structures, where ultra low dielectric constants are required to decrease the parasitic capacitances between metal lines. Porous material, obtained using the porogen approach, is the main candidate investigated. The curing process is critical for achieving a good control of final film structure. The integration of such material requires a good chemical and mechanical stability, particularly to maintain the structure integrity during the stressing steps: chemical mechanical polishing and packaging. In this work, Ultraviolet assisted thermal cure (or UV curing) is investigated as an alternative solution to the conventional thermal curing. Chemical and physical analyses reveal that the best porogen removal efficiency and the enhancement of matrix crosslinking are achieved when the material is UV cured. This crosslinking improvement (as indicated by higher Si–O–Si bond density in the fourier transformed infra-red spectra) can be correlated to better mechanical properties. Significantly better electrical properties (dielectric constant, leakage current and breakdown voltage) are obtained with better integrity (no moisture uptake after 1 week storage in humid atmosphere 85 °C/85% relative humidity) when the dielectric is optimally cured. Porosity evaluation reveals similar results between both curing processes with slightly larger pore size in the case of the UV cured film. Finally, a basic model is described to illustrate how the UV assisted thermal cure may improve the crosslinking in comparison to the thermal curing. Selective UV action is proposed to explain the curing process kinetics.
    Thin Solid Films 01/2008; 516(6):1097-1103. · 1.87 Impact Factor
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    ABSTRACT: To improve integrated circuit performance, microelectronic chip interconnections need dielectric materials with ultralow k (ULK) values. Porous a- Si O C H , an ULK material, can be created using a two step strategy called a porogen approach. The first step consists of a hybrid film deposition, which is an a- Si O C H matrix containing an organic sacrificial phase. Afterwards, the organic phase is removed during a post-treatment to generate the porosity. In this work, hybrid deposition was performed by plasma enhanced chemical vapor deposition and the post-treatment was a thermal annealing. Firstly, hybrid films with different a- Si O C H matrix structures were created using two matrix precursors [decamethylcyclopentasiloxane (DMCPS) and diethoxymethylsilane (DEMS)] and an O <sub>2</sub> addition in a plasma gas feed. For the same porogen loading, the shrinkage behavior during the porogen removal is correlated to the matrix structure. Fourier transform infrared spectroscopy and <sup>29</sup> Si solid nuclear magnetic resonance are both used to determine the structure. The O <sub>3</sub> Si  Me <sub>1</sub> is favorable to prevent high film shrinkage and the O <sub>2</sub> Si  Me <sub>2</sub> leads to high film shrinkage and absence of porosity generation. To prevent the existence of this type of structure, DEMS + O <sub>2</sub> appears more appropriate as a matrix precursor than DEMS only or DMCPS. Secondly, using the appropriate matrix structure, the influence of th- e porogen loading on the porosity creation is studied. Hybrids with different porogen loadings are achieved by changing the porogen precursor ratio in the plasma gas feed. The porogen conversion into porosity is studied for different porogen loadings and the results indicate the existence of a porogen loading threshold. Above it, there is no more porosity generation because of the too high film shrinkage during the porogen removal. This behavior is explained by a too low matrix ratio in the hybrid film. For the high porogen loadings, the matrix skeleton (mainly constituted by Si  O  Si bridging bonds) is not in sufficient quantity to prevent such film shrinkage. The porous a- Si O C H created with the most favorable matrix structure and porogen loading has the ultralow k value of 2.3.
    Journal of Applied Physics 10/2007; · 2.21 Impact Factor
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    ABSTRACT: A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.
    International Interconnect Technology Conference, IEEE 2007; 07/2007
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    ABSTRACT: An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.
    International Interconnect Technology Conference, IEEE 2007; 07/2007
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    ABSTRACT: The introduction of air gaps in multi-level Cu interconnect stacks will be mandatory to achieve high performance signal propagation characteristics for advanced technology node. In this paper, air cavities were successfully introduced in a two-metal level interconnect stack using respectively a polymer and a sacrificial SiO<sub>2</sub> at via and metal levels. Combined with a diluted HF chemistry and specific HF diffusion pathways patterned in a SiC liner, the ability to localize the introduction of air cavities in a dedicated large electrical area was demonstrated. Electrical characteristics and mechanical simulations demonstrated the interest of the approach with respect to ultra-low K material integration issues.
    International Interconnect Technology Conference, IEEE 2007; 07/2007
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    ABSTRACT: Self-aligned barriers (SAB) are investigated for the 45nm technology node and beyond to improve copper electromigration and stress-migration resistance. The impact of plasma and cleaning processes used in the integration were studied on CoWPB-SAB. Results extracted from complementary characterizations show that after fluorocarbon-based and/or oxidizing plasmas, CoWPB is slightly etched and a less dense zone is formed at the CoWPB surface. This zone is not protective during cleaning: CoWPB is alterated by diluted HF solution leading to pits at the surface and crystals for the samples treated by fluorocarbon-based plasma. Pitting corrosion can be caused by the dissolution of one of the two phases existing in the CoWPB: amorphous and crystalline. The solubility of these phases depends on their thermodynamic equilibrium in solution and their reaction kinetics with HF.
    Microelectronic Engineering - MICROELECTRON ENG. 01/2007; 84(11):2455-2459.
  • Journal of The Electrochemical Society - J ELECTROCHEM SOC. 01/2007; 154(1).
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    ABSTRACT: With the downscaling of feature dimensions, each layer of the metallization stack has to become thinner and thinner to comply with the geometrical constraints. In particular, seed layer thickness will have to be drastically reduced for the 45nm node and beyond. As PVD is a non-conformal technique, discontinuous seeding of the sidewalls of narrow features can be expected. In this study, a seed layer enhancement (SLE) process is evaluated for 300mm processing, as a possible solution for copper seeding for the 45nm node and below. We demonstrate the extendibility of this process to the fabrication of 300mm wafers. We confirm the excellent morphological properties of the deposit, which is extremely conformal, thus continuous inside the features. This process is successfully integrated in the existing metallization sequence, without any modification of the subsequent steps, including electroplating. This demonstration is supported by electrical results, showing that a 10nm thick PVD liner, which leads to severe degradation of line and via resistance, is efficiently repaired with only 20nm SLE. All electrical performances (line and via resistance, dispersion and yield) are fully recovered with implementation of the SLE step.
    Microelectronic Engineering - MICROELECTRON ENG. 01/2007; 84(11):2610-2614.

Publication Stats

198 Citations
24.08 Total Impact Points

Institutions

  • 2008
    • Atomic Energy and Alternative Energies Commission
      Fontenay, Île-de-France, France
  • 2007–2008
    • STMicroelectronics
      Genève, Geneva, Switzerland
  • 1998–2005
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2000
    • University of Strasbourg
      • Institut Charles Sadron
      Strasbourg, Alsace, France