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L. K. Wang,
J. Silverman,
D. Seeger,
E. Petrillo,
V. DiMilia,
D. Katcoff,
K. Kwietniak,
R. Acosta,
K. Petrillo,
S. Brodsky, [......],
O. Vladimirsky,
H. Voelker,
R. Viswanathan,
J. Warlaumont,
A. Wilson,
R. Devenuto,
B. Hill, L. C. Hsia,
R. Rippstein,
C. Wasik
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ABSTRACT: High performance fully scaled 0.5 μm complementary metal–oxide semiconductors very large scale integrated (CMOS VLSI) circuits have been fabricated using synchrotron x‐ray lithography technology. X‐ray lithography is employed at all levels to attain a minimum feature size of 0.5 μm. The wafer exposures are done at the VUV storage ring from the National Synchrotron Light Source, Brookhaven National Laboratory. A stepper built at IBM Yorktown Heights is used at the beamline to perform the wafer exposures. All the lithography levels are aligned to the prefabricated 0.5 μm deep silicon trench zero level with an overlay less than 0.1 μm (1σ) between levels. Single level resists (both positive and negative) are used throughout the entire CMOS process. Linewidth control better than 0.01 μm and alignment tolerance less than 0.10 μm are accomplished. The patterning of this x‐ray lithography mask is accomplished through a vector scan electron beam direct writing system. Masks made of boron doped silicon membranes with electroplated gold are used as the absorber. An average linewidth variation less than 0.2 μm can be attained for the (25 mm)<sup>2</sup> field size masks. A retrograded N well 0.5 μm CMOS process is used to exercise the fabrication of x‐ray lithography VLSIs. In the (25 mm)<sup>2</sup> testsite, CMOS devices, ring oscillators and fully scaled 0.5 μm CMOS SRAM (static random access memory) are densely populated to exercise this technology. In this experiment CMOS devices and ring oscillators are successfully fabricated. The device characteristics are essentially the same as those fabricated using other lithography methods. A fully scaled 0.5 μm 61 stage inverter ring oscillator was measured at a delay of 95 ps/stage when operating at a 3.5 volts power supply. Radiation effects on the fabricated CMOS devices are studied. With the final 400 -
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°C hydrogen ambient annealing, there is no apparent difference on the device characteristics in comparison to the same devices fabricated using optical lithography.
Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 12/1989; · 1.34 Impact Factor
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J. P. Silverman,
V. DiMilia,
D. Katcoff,
K. Kwietniak,
D. Seeger,
L. K. Wang,
J. M. Warlaumont,
A. D. Wilson,
D. Crockatt,
R. Devenuto,
B. Hill, L. C. Hsia,
R. Rippstein
[show abstract]
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ABSTRACT: Functional, fully scaled n‐type metal–oxide semiconductor (NMOS) circuits with 0.5‐μm ground rules have been fabricated using synchrotron radiation x‐ray lithography for all device levels. The exposures were done at the vacuum ultraviolet storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The system is capable of step‐and‐repeat exposures covering 125‐mm wafers. The mask and wafer are held in a near‐vertical plane and a scanning dark‐field alignment technique is used to register mask to wafer with a proximity gap of 40 μm. A scanning mirror in the beamline sweeps the x‐ray beam up and down over the exposure area to achieve uniform exposure over the 25×25 mm<sup>2</sup> exposure field used for this experiment. Exposures were done in 20 Torr of helium to provide cooling for the mask. Both positive and negative tone single‐layer resists were used. The mask set consists of four light‐field masks patterned on silicon substrates with electroplated gold absorbers; patterns were written by a vector scan electron beam lithography system. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay and linewidth control. The repeatability of the alignment and the overall level‐to‐level overlay are described. Characteristics of the fabricated devices are also presented.
Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 12/1988; · 1.34 Impact Factor
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[show abstract]
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ABSTRACT: Functional NMOS and CMOS circuits with fully-scaled 0.5 μm ground rules have been fabricated using synchroton radiation X-ray lithography for all device levels. The exposures were done at the VUV storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay. Characteristics of the fabricated circuits are also presented.
Microelectronic Engineering.
