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ABSTRACT: In recent years, scaled CMOS technologies have led to an increased cell functional density and a better spatial resolution in monolithic active pixel sensors (MAPS) for vertexing applications. Advanced MAPS may also take advantage of CMOS process features such as the deep n-well (DNW) structure, which can be used as the charge collecting element of the detector. A new kind of DNW-MAPS, namely SDR1, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. 3D processes may offer significant advantages in terms of detection efficiency, pixel cell size and immunity from cross-talk, therefore complying with the severe constraints set by future HEP experiments. This work includes a description of the analog and digital circuits integrated in the SDR1 chip, together with circuit simulations. Device simulation results concerning detection efficiency will be also discussed.
PoSVERTEX. 01/2009;
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ABSTRACT: This work is concerned with the design of time invariant analog circuits for processing the signals from deep n-well monolithic CMOS sensors. As compared to the three-transistor front-end typically used in imaging applications, the schemes proposed here, which were conceived to be included in a binary readout channel, lend themselves to pixel-level sparsified readout and are expected to be capable of managing the large flow of data anticipated for the future high luminosity colliding machines. Various solutions complying with different power dissipation and point resolution constraints have been implemented in a 130 nm CMOS technology, paying particular attention to equivalent noise charge and threshold dispersion performance. This paper intends to describe and compare the features of the different approaches by means of theoretical analysis, simulation and experimental results.
Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE; 11/2008
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ABSTRACT: This paper is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron technology for use in charged particle trackers and vertex detectors. In such devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. This paper will discuss the design and performance of a deep N-well (DNW) monolithic sensor prototype including different test structures with both analog and digital functions. The paper also reports results from physical device simulations, aiming at evaluating the properties of the DNW sensor in terms of charge diffusion and charge sharing among pixels.
PoSVertex. 01/2007;
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ABSTRACT: This study is concerned with the simulation and design of low-noise front-end electronics monolithically integrated on the same high-resistivity substrate as multielectrode silicon detectors, in a process made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST) of Trento, Italy. The integrated front-end solutions described in this paper use N-channel JFETs as basic elements. The first one is based upon an all-NJFET charge preamplifier designed to match detector capacitances of a few picofarads and available in both a resistive and a non resistive feedback configuration. In the second solution, a single NJFET in the source-follower configuration is connected to the detector, while its source is wired to an external readout channel through an integrated capacitor.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
12/2001;
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ABSTRACT: This work will discuss the design of analog circuits for processing the signals from deep N-well monolithic CMOS sensors and from high resistivity substrate pixel detectors. Several options for the design of the SuperB Layer0 are being studied. Hybrid pixel detectors are nowadays a robust and mature technology for the innermost vertex detector layer, but they require a relatively large material budget which can make them marginal for the foreseen application. CMOS MAPS technology has the potential for providing very thin detectors since the sensor and the readout electronics are integrated in the same substrate. Recently, a very promising approach to MAPS based on the use of a vertically integrated CMOS technology has also been considered. Various solutions complying with different S/N ratio and detector capacitance constraints have been studied and implemented in a planar 130nm CMOS technology and in a 130nm CMOS technology with vertical integration capabilities. This paper intends to describe and compare the features of the different options by means of simulations and experimental results.
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ABSTRACT: In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source (55Fe) tests, will be presented.
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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ABSTRACT: The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13 μm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments (SLHC, ILC, Super B-Factory).
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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ABSTRACT: This paper is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130 nm minimum feature size) for use in charged particle trackers and vertex detectors. As compared to conventional MAPS with 3-transistor readout scheme, the design approach proposed here, where a deep N-well (DNW) is used as the collecting electrode, lends itself to pixel-level sparsified processing and is expected to provide the ability to manage the large data flow of information anticipated for future, high luminosity colliders. Lately, the applicability of the DNW-MAPS concept to the design of the vertex detector for future high luminosity colliders, like the International Linear Collider (ILC), has been investigated. This paper will discuss the design and performance of a recently submitted DNW monolithic sensor, the SDR0 (Sparsified Digital Readout) chip, including different test structures, where both analog (charge amplification and threshold discrimination) and digital (sparsification, time stamping) functions have been integrated inside the elementary sensor, as large as .
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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ABSTRACT: 130 nm and 90 nm CMOS processes are going to be used in the design of mixed-signal integrated circuits for the readout of detectors in the future generation of HEP experiments. In applications such as inner SLHC detectors, these ultra-deep submicron systems will have to stand total doses of ionizing radiation of the order of 100 Mrad and beyond. While the scaling of the gate oxide thickness to about 2 nm gives a high degree of radiation tolerance, issues such as the gate tunneling current and the sidewall leakage associated to lateral isolation oxides must be investigated. This paper provides an analysis of an extensive set of irradiation tests carried out on 130 and 90 nm CMOS transistors belonging to commercial technologies. With special focus on the design of analog front-end circuits for silicon pixel and strip detectors, the impact of ionizing radiation on the noise performance is evaluated and the underlying physical degradation mechanisms are pointed out to provide criteria for improving radiation hardness properties.
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
