L. Ratti

University of Pavia, Ticinum, Lombardy, Italy

Are you L. Ratti?

Claim your profile

Publications (186)160.29 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: The chip prototype Apsel4well, including monolithic active pixel sensor (MAPS) test structures, has been designed for vertexing applications requiring a fast and low material silicon vertex tracker. The chip is fabricated in a 180 nm CMOS process called INMAPS, featuring a quadruple well and a high resistivity epitaxial layer option. The main advantage with this approach lies in the chance of increasing the in-pixel intelligence as compared to standard three transistor MAPS schemes. Moreover, the presence of the quadruple well and of the high resistivity epitaxial layer leads to better charge collection performance and radiation resistance. Different samples of the Apsel4well chip have been thinned down to about 25 $mu$m and 50 $mu$m. This minimization of the material can further improve the tracker performance virtually with no charge signal loss. At the beginning, this paper focuses on the results from charge collection TCAD simulations of the Apsel4well pixel structure performed at different thicknesses and substrate bias voltages. Later on, results from measurements relevant to the thinned chips both in terms of analog front-end channel performance and charge collection properties will be shown and compared to those from non-thinned chips.
    IEEE Transactions on Nuclear Science 04/2014; 61(2):1039-1046. · 1.46 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.
    IEEE Transactions on Nuclear Science 01/2014; 61(1). · 1.46 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on radiation tolerance and damage mechanisms. Measurements of static characteristics and noise voltage spectra before and after exposure to high total ionizing doses demonstrate that the analog performance of transistors as well as their radiation hardness are not degraded by mechanical and thermal stresses occurring during the fabrication of the 3D chips. The paper also presents irradiation results on 3D CMOS pixel sensors with a sparsified readout architecture. After exposure to ionizing radiation, these devices behave in a very similar way as analogous counterparts in a standard 2D 130-nm process, confirming that performance advantages associated with 3D integration are not impaired by an enhanced radiation sensitivity.
    IEEE Transactions on Nuclear Science 12/2013; 60(6):4526-4532. · 1.46 Impact Factor
  • Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 12/2013; · 1.32 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The development of an innovative position sensitive pixelated sensor to detect and measure with high precision the coordinates of the ionizing particles is proposed. The silicon avalanche pixel sensors (APiX) is based on the vertical integration of avalanche pixels connected in pairs and operated in coincidence in fully digital mode and with the processing electronics embedded on the chip. The APiX sensor addresses the need to minimize the material budget and related multiple scattering effects in tracking systems requiring a high spatial resolution in the presence of a large occupancy. The expected operation of the new sensor features: low noise, low power consumption and suitable radiation tolerance. The APiX device provides on-chip digital information on the position of the coordinate of the impinging charged particle and can be seen as the building block of a modular system of pixelated arrays, implementing a sparsified readout. The technological challenges are the 3D integration of the device under CMOS processes and integration of processing electronics.
    Journal of Instrumentation 11/2013; 9(03). · 1.53 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents the results of the characterization of novel CMOS active pixel sensors that take advantage of 3D integration to increase the electronic functions in the pixel readout cells. These sensors were designed in the frame of an R&D program targeting applications to high energy physics experiments at advanced particle accelerators. They were fabricated with the Tezzaron/GlobalFoundries 3D process, which makes it possible to build two-tier integrated circuits by the face-to-face bonding of two 130 nm CMOS wafers. High-density “via middle” TSVs and small-pitch Cu-Cu interconnections between tiers make this process suitable for aggressive mixed-signal circuit design.
    2013 IEEE International 3D Systems Integration Conference (3DIC); 10/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A model, approximating minority carrier diffusion with a discrete random walk and accounting for radiation induced reduction of minority carrier lifetime, is proposed to predict the effects of neutron irradiation on the charge collection properties of monolithic active pixel sensors (MAPS) in CMOS technology. The model has been implemented in a Monte Carlo code to simulate MAPS operation in minimum ionizing particle detection systems. For the purpose of validating it, the results from the characterization of monolithic sensors irradiated up to an integrated fluence of 1014 1- MeV-neutron equivalent/cm2 have been compared with the outcomes of the Monte Carlo simulations. The monolithic sensors taken into consideration for the model validation are based on two different CMOS processes, one featuring a triple well option, the other one featuring a quadruple well structure and a standard (10 Ω·cm) or high (1 kΩ·cm) resistivity epitaxial layer. Simulation results are shown to be in good agreement with experimental data. The consistency between the model and the measurement results seems to confirm that radiation induced increase in the recombination rate is the main source of charge collection degradation in neutron-irradiated MAPS.
    IEEE Transactions on Nuclear Science 08/2013; 60(4):2574-2582. · 1.46 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this Technical Design Report (TDR) we describe the SuperB detector that was to be installed on the SuperB e+e- high luminosity collider. The SuperB asymmetric collider, which was to be constructed on the Tor Vergata campus near the INFN Frascati National Laboratory, was designed to operate both at the Upsilon(4S) center-of-mass energy with a luminosity of 10^{36} cm^{-2}s^{-1} and at the tau/charm production threshold with a luminosity of 10^{35} cm^{-2}s^{-1}. This high luminosity, producing a data sample about a factor 100 larger than present B Factories, would allow investigation of new physics effects in rare decays, CP Violation and Lepton Flavour Violation. This document details the detector design presented in the Conceptual Design Report (CDR) in 2007. The R&D and engineering studies performed to arrive at the full detector design are described, and an updated cost estimate is presented. A combination of a more realistic cost estimates and the unavailability of funds due of the global economic climate led to a formal cancelation of the project on Nov 27, 2012.
    06/2013;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The Apsel4well monolithic active pixel sensor (MAPS) chip prototype is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks related to three transistors MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to further improvements in terms of charge collection performance and radiation resistance. This paper, after giving some hints on the INMAPS process, focuses on the analog front-end section of the pixel readout chain. Measurement results on the main analog channel performance, like charge sensitivity and equivalent noise charge, are given along with charge collection efficiency evaluation through laser stimulation. These last characterization data were also used for validating TCAD simulation results of the sensor charge collection performance. Finally, results from a neutron irradiation campaign performed with fluences up to 2.7 × 1013 1 MeV neutron equivalent/cm2 will be shown and compared with the outcome of a Monte Carlo charge loss model of the structure useful for the rad-harder design of the next quadruple well MAPS.
    2012 IEEE Nuclear Science Symposium and Medical Imaging Conference (2012 NSS/MIC); 10/2012
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.
    Journal of Instrumentation 02/2012; 7(02):C02007. · 1.53 Impact Factor
  • Lodovico Ratti, Alessia Manazza
    [Show abstract] [Hide abstract]
    ABSTRACT: This work is intended to provide a set of guidelines for the design of digital-to-analog converters enabling the reduction of threshold dispersion in multichannel readout circuits for radiation detectors. The design criteria are first established through a theoretical approach and then confirmed by means of a simulation tool based on Monte Carlo methods. This latter tool provides a fast and flexible way to predict the performance of a DAC for threshold correction, also accounting for possible non-idealities, such as differential and integral non linearities and gain and offset errors. The proposed guidelines have been validated through simulations on front-end circuits for a real application, the silicon vertex tracker for the SuperB Factory, and through comparison with data available in the literature.
    IEEE Transactions on Nuclear Science 02/2012; 59(1):144-153. · 1.46 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.
    01/2012;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45^o angle to the detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2012; Conference: C12-05-20 Proceedings. · 1.32 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This work is concerned with the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for a possible future upgrade of the SuperB-Layer0, is provided through a complete characterization of the prototypes, including tests with infrared (IR) laser, 55Fe and 90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 01/2012; · 1.32 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The SuperB factory is an Italian e+ e- accelerator project that plans to reach a luminosity higher than 1036 cm-2s-1 by means of a very small beam size and with moderate beam currents. To achieve the performance imposed by physics, six layers of microstrip silicon sensors, with different pitches and lengths, are foreseen in the present design of the Silicon Vertex Tracker (SVT). The SuperB SVT readout chip for inner Layers (L0-L3) is a 128-channel mixed-signal integrated circuit in a 130 nm CMOS technology. Each channel consists of a charge-sensitive preamplifier, a second order unipolar semi-Gaussian shaper, a baseline restorer and a hit discriminator. A 4 bit A/D conversion will be performed by means of the Time-Over-Threshold (ToT) technique. This paper presents the solutions adopted in this chip for the analog channel building blocks and discusses the simulation results for the current design along with the expected performance in terms of parameters such as signal-to-noise ratio, dynamic range, linearity, power dissipation and hit time resolution.
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: Three-dimensional monolithic pixel sensors have been designed following the same approach that was exploited for the development of the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous layers fabricated in a 130 nm CMOS technology. One of the two tiers, which are face-to-face bonded, has to be thinned down to about to expose the through silicon vias connecting the circuits to the back-metal bond pads. As a consequence of the way the two parts of each single chip are designed and fabricated, the prototypes of the 3D monolithic detector will include both samples with a thick substrate underneath the collecting DNW electrode, suitable for charged particle tracking, and samples with a very thin (about ) sensitive volume, which may be used to detect low energy particles in biomedical imaging applications. Device physics simulations have been performed to evaluate the collection properties and detection efficiency of the proposed vertically integrated structures.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 10/2011; 652(1):630-633. · 1.32 Impact Factor
  • Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 09/2011; 650(1):169–173. · 1.32 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/f and white noise terms is studied as a function of the main device parameters before and after exposure to 10keV X-rays and 60Co γ-rays. A prototype chip designed in a 65nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.
    Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 09/2011; 650(1):163-168. · 1.32 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model involving charge buildup in shallow trench isolations and lateral parasitic transistor activation. Comparison between two CMOS processes both belonging to the 90 nm node but coming from different foundries makes it possible to shed some light on the process-dependent features of the device response to ionizing radiation.
    IEEE Transactions on Nuclear Science 07/2011; · 1.46 Impact Factor

Publication Stats

1k Citations
160.29 Total Impact Points

Institutions

  • 2000–2012
    • University of Pavia
      • Department of Electrical, Computer and Biomedical Engineering
      Ticinum, Lombardy, Italy
  • 2002–2011
    • University of Bergamo
      • Department of Engineering
      Bérgamo, Lombardy, Italy
  • 1999–2011
    • INFN - Istituto Nazionale di Fisica Nucleare
      Frascati, Latium, Italy
  • 2008
    • Università Politecnica delle Marche
      Ancona, The Marches, Italy
  • 2007
    • University of Bologna
      Bolonia, Emilia-Romagna, Italy
    • University of Milan
      • Department of Physics
      Milano, Lombardy, Italy
  • 2003–2006
    • Università degli Studi di Trento
      • Department of Information Engineering and Computer Science
      Trient, Trentino-Alto Adige, Italy
  • 2005
    • Università degli Studi di Siena
      Siena, Tuscany, Italy
  • 1999–2004
    • Lawrence Berkeley National Laboratory
      Berkeley, California, United States
  • 2001
    • Museo delle Scienze, Trento, Italy
      Trient, Trentino-Alto Adige, Italy