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ABSTRACT: The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO<sub>2</sub> or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent variability. Conventional reliability margins, based on accelerated stress measurements on individual transistors, are no longer sufficient nor adequate for analog circuit design. As a means to find more accurate, circuit-dependent reliability margins, advanced degradation effect models are reviewed and an efficient method for stochastic circuit reliability simulation is discussed. Also, an example 6-bit 32nm current-steering digital-to-analog converter is studied. Experiments demonstrate how the proposed simulation tool, combined with novel design techniques, can provide an up to 89% better area-power product of the analog part of the circuit under study, while still guaranteeing a 99.7% yield over a lifetime of 5 years.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011; 04/2011
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ABSTRACT: Stochastic circuit reliability analysis, as described in this work, matches the statistical attributes of underlying device fabrics and transistor aging to the spatial and temporal reliability of an entire circuit. For the first time, spatial and temporal stochastic and deterministic reliability effects are handled together in an efficient framework. The paper first introduces an equivalent transistor SPICE model, comprising the currently most important aging effects (i.e NBTI, hot carriers and soft breakdown). A simulation framework then uses this SPICE model to minimize the number of circuit factors and to build a circuit model. The latter allows for example very fast circuit yield analysis. Using experimental design techniques the proposed method is very efficient and also proves to be very flexible. The simulation technique is demonstrated on an example 6-bit current-steering DAC, where the creation of soft breakdown spots can result in circuit failure due to increasing time-dependent transistor mismatch.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011; 04/2011
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ABSTRACT: Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on. 04/2011;
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ABSTRACT: This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2011; · 1.27 Impact Factor
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ABSTRACT: A complete and comprehensive physics-based model for negative bias temperature instability (NBTI) reliability simulation of analogue circuits in nanometre CMOS technologies is proposed. It includes typical NBTI peculiarities, such as relaxation after voltage stress reduction, and dependence on time-varying voltage stress, temperature and frequency. Including both the recoverable and the permanent NBTI component, the model offers a significant accuracy improvement over existing compact models. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Additionally, the model includes only 10 process-dependent parameters, enabling easy calibration. The model was validated on a 1.4 EOT CMOS process.
Electronics Letters 10/2010; · 0.96 Impact Factor
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ABSTRACT: With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.
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ABSTRACT: Channel hot carrier (CHC) degradation is one of the major reliability concerns for nanoscale transistors. To simulate the impact of CHC on analog circuits, a unified analytical model able to cope with various design and process parameters is proposed. In addition, our model can handle initial degradation and varying stress conditions, allowing the designer to estimate the impact of CHC on transistor performance for arbitrary stressing patterns. The model is experimentally verified in a 65 nm CMOS technology. Expressions to simulate the impact of transistor degradation on relevant transistor parameters like output conductance and threshold voltage degradation are presented and verified.
Microelectronics Reliability.
