K.P. Roenker

University of Cincinnati, Cincinnati, OH, United States

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Publications (67)84.31 Total impact

  • Aniket A. Breed, Kenneth P. Roenker
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    ABSTRACT: As MOSFET scaling pushes channel lengths below 65nm, device designs utilizing fully depleted silicon-on-insulator (SOI) technology and employing two or more gates are becoming increasingly attractive as a means to counteract short channel effects. The presence of multiple gates enhances the total control that the gate exercises on the channel region and the SOI technology allows for a significant reduction in the junction capacitance. In combination, these two factors result in devices that exhibit superior characteristics to the conventional planar MOSFET. This paper compares the variation in the switching performance of the three leading multi-gate MOSFET designs, namely the FinFET, TriGate, and Omega-gate. A 3-dimensional, commercial numerical device simulator is employed to investigate the device characteristics using a common set of material parameters, device physics models, and performance metrics. Examined initially are the short-channel effects including the subthreshold slope (S) and the drain-induced barrier lowering as the gate length is scaled down to 20nm. Subsequently investigated and compared are the effects of scaling of the fin’s body width and height, the oxide thickness, and channel doping. The investigation reveals that the Omega-gate MOSFET shows the best scaling characteristics at a particular device dimension with the TriGate device showing the least variation in characteristics as device dimensions vary.
    Analog Integrated Circuits and Signal Processing 07/2008; 56(1):135-141. · 0.55 Impact Factor
  • Saumitra R Mehrotra, K.P. Roenker
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    ABSTRACT: This paper examines the sensitivity of silicon nanowire transistors to process variations. Silicon nanowire MOSFETs are effective in controlling short channel effects, but at the same time suffer from threshold voltage degradation due to the quantum confinement effect. In this study we have investigated the effects on the device characteristics of process variations due to body thickness, gate length and gate dielectric thickness. The results have been compared with previous results for the FinFET and the differences quantified. The nanowire MOSFET is found to exhibit significantly less short channel effects relative to a comparable FinFET structure, but to have a larger threshold voltage variation with the diameter at a diameter less than 4 nm.
    Microelectronics and Electron Devices, 2007. WMED 2007. IEEE Workshop on; 05/2007
  • A.A. Ahmadain, K.P. Roenker, K.A. Tomko
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    ABSTRACT: Using the nanoMOS 2.5 simulator, we study the impact of varying the channel length, gate oxide thickness and dielectric constant, drain voltage, and temperature on the performance of a ballistic nanoscale MOSFET using quantum ballistic and classic ballistic transport models. Our key results show that the quantum ballistic (QB) transport model typically predicts a lower on-state current compared to the classical ballistic (CB) model except for a 5nm channel length where source-to-drain tunneling contributes approximately 35% to the on-state current. We also show that the off-state current is significantly affected by the gate oxide thickness, whereas the influence of varying the oxide dielectric constant on the off-state current was not as pronounced for a 1.5nm oxide thickness. Finally, we show that room temperature operation (T=300K) leads to an excessively high off-state current and a degraded subthreshold slope. For low temperatures, (T=100K), the QB and CB models predicts a seven orders of magnitude difference in the off-state current.
    Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on; 07/2006
  • A. Breed, K.P. Roenker
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    ABSTRACT: This paper compares the scaling characteristics of the three leading multi-gate MOSFET designs, namely the finFET, trigate and omega-gate. A commercial numerical device simulator is employed using a common set of material parameters, device physics models and performance metrics. Examined initially are the short channel effects including the subthreshold slope S and drain induced barrier lowering DIBL as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin body's width and height, the oxide thickness and the channel doping. The results suggest that the omega-gate MOSFET shows the best device scaling characteristics.
    Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005
  • A. Breed, K.P. Roenker
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    ABSTRACT: This paper examines the performance and scaling characteristics of p-channel silicon FinFETs (pFinFETs) using three dimensional device modeling based on a drift-diffusion model. A commercial numerical device simulator was employed to investigate the device's short channel effects down to a channel length of 20 nm. The results show that the pFinFET provides good scaling characteristics with the subthreshold slope increasing from 66 mV/dec to 76 mV/dec and the drain induced barrier lowering from 17 m V/V to 80 m V/V as the gate length decreases from 80 to 20 nm's. Subsequently, the performance of the pFinFET at high frequencies was examined for a gate length of 50 nm with promising results. Peak values of the cutoff frequency fT and maximum frequency of oscillation fmax of 53 GHz and 211 GHz, respectively, were obtained as the gate bias was swept. These preliminary results indicate the potential for high peiformance pFINFETs.
    Circuits and Systems, 2005. 48th Midwest Symposium on; 01/2005
  • R. Sampathkumaran, K.P. Roenker
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    ABSTRACT: In this study, the effects of self-heating on the fT and fmax frequencies have been investigated in NpN SiGe heterojunction bipolar transistors (HBTs) by two-dimensional numerical device modeling using a commercial simulator. The device studied was a single emitter stripe, double mesa configuration with self-aligned base contacts where a Gaussian distribution was assumed for the base’s boron profile. Increases in the base transit time and the collector delay time due to degradation in the electron mobility and saturation velocity and an increase in the base-collector depletion layer width were found to degrade the fT while increased base resistance also contributed to the reduction in fmax. The onset of significant device self-heating and degradation in fT and fmax were observed for collector current densities of 5 × 104 A/cm2 for VCE = 2 V.
    Solid-State Electronics 01/2005; · 1.48 Impact Factor
  • A.A. Breed, K.P. Roenker
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    ABSTRACT: Because of their superior scaling characteristics and reduced short channel effects, multi-gate MOSFETs are being considered for replacing conventional planar silicon MOSFETs in digital applications. At the same time, improvements in the high frequency capabilities of conventional MOSFETs have made them increasingly attractive for RF applications. The paper examines the performance capabilities of multi-gate MOSFETs in the RF regime using a simulation study of their small-signal behavior. Three dimensional numerical simulations have been performed to investigate the high frequency performance of two of the most promising multigate devices, i.e. the finFET and the trigate transistor. The trigate transistor has been found to exhibit a higher transconductance, small signal current gain and unilateral power gain as compared to the finFET, as well as a higher cutoff frequency, f<sub>T</sub>, and maximum frequency of oscillation, f<sub>MAX</sub>. Peak f<sub>T</sub> of 42 and 51 GHz and peak f<sub>MAX</sub> of 183 and 228 GHz were obtained for the finFET and trigate transistors, respectively, for a gate length of 50 nm.
    Silicon Monolithic Integrated Circuits in RF Systems, 2004. Digest of Papers. 2004 Topical Meeting on; 10/2004
  • A. Breed, K.P. Roenker
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    ABSTRACT: The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.
    Semiconductor Device Research Symposium, 2003 International; 01/2004
  • S. Srivastava, K.P. Roenker
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    ABSTRACT: A one dimensional, drift-diffusion based, analytical model is reported which describes the operation and performance of the InP-based uni-traveling carrier photodiode (UTC-PD). The UTC-PD has been proposed as a replacement for the InGaAs PIN photodiode for long wavelength optical communications. In this work, the development of an analytical model is described for use in investigation of the device's operation and the effects of the device structure on the operational performance of the device. The effects of a finite conduction band barrier at the collector end of the absorption layer on the photocurrent and onset of high injection effects is examined. Also included in the model is the leakage current due to a finite conduction band barrier at the blocking end of the absorption layer. The results are discussed in relation to reports of the device's experimentally observed performance and numerical modeling results.
    Semiconductor Device Research Symposium, 2003 International; 01/2004
  • P.A. Balaraman, K.P. Roenker
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    ABSTRACT: Device modeling using a two dimensional, drift-diffusion approach utilizing a commercial numerical device simulator has been used to investigate the operation and performance of InP/GaAsSb heterojunction bipolar transistors (HBTs). GaAsSb lattice matched to InP has an energy bandgap (0.72 eV) that is similar to that of InGaAs (0.75 eV) so that Sb-based HBTs have been proposed as a replacement for InGaAs-based HBTs. In particular, the conduction band lineup is more favorable at the base-collector, which makes the GaAsSb-based HBTs especially attractive for double heterojunction bipolar transistors (DHBTs) where higher breakdown voltages are desired. In this work, the results of device modeling will be compared initially with recent experimental reports to validate the modeling approach. Subsequently, the design and operation of the devices will be examined to investigate the factors controlling device performance in order to facilitate improvements in device design.
    Semiconductor Device Research Symposium, 2003 International; 01/2004
  • D. Prentice, K.P. Roenker
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    ABSTRACT: The operation and performance of the organic, pentacene-based MOSFETs has been studied using a two dimensional, drift-diffusion approach utilizing a commercial numerical device simulator. Organic semiconductors have been proposed as a replacement for amorphous or polycrystalline-based silicon devices for low cost applications such as RF tags and display drivers. While extensive experimental development of these devices has proceeded, their study using device modeling has received comparatively little attention. In this work, the results of device modeling using a commercial simulator will be compared with the experimental reports for pentacene-based, p-channel MOSFETs for both bottom and top contact geometries. The results demonstrate that commercial simulators can be used to model these devices in spite of the nontraditional nature of the hole transport in organic semiconductors.
    Semiconductor Device Research Symposium, 2003 International; 01/2004
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    S. Srivastava, K. P. Roenker
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    ABSTRACT: The operation and performance of the InP-based uni-traveling carrier photodiode (UTC-PD) has been studied using a two dimensional, drift–diffusion approach utilizing a commercial numerical device simulator. The UTC-PD has been proposed as a replacement for the InGaAs PIN photodiode for long wavelength optical communications since it retains its performance at high levels of optical injection and exhibits a very high frequency capability. In this work, the results of an investigation of the effects of the device’s structure on the operational performance are reported as well as the effects of device biasing and the optical injection level. In particular, the origins of the degradation in device performance at high optical injection levels have been investigated. The results are discussed in relation to reports of the device’s experimentally observed performance.
    Solid-State Electronics 01/2004; 48(3):461-470. · 1.48 Impact Factor
  • K. P. Roenker, R. Sampathkumaran, A. Breed
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    ABSTRACT: The design of SiGe heterojunction bipolar transistors for high frequency (10 GHz), high power applications has been investigated by numerical device modelling using a commercial simulator. For the SiGe base layer, boron outdiffusion can give rise to displacement of the base-collector p-n junction from the collector heterojunction, which contributes to the development of a parasitic barrier in the conduction band. In this paper, using a Gaussian distribution for the base's boron profile, we examine the effects of the device's epitaxial layer design on the device's unilateral power gain at 10 GHz and its relation to this barrier. Degradation in the device's microwave power gain was found to correlate with formation of the collector junction parasitic barrier, where the barrier height was found to depend upon the extent of the p-n junction displacement from the heterojunction, the Ge concentration in the base and the dc bias point. Trade-offs in device design to reduce its sensitivity to outdiffusion were examined including the use of undoped SiGe spacer layers, increased collector doping and the insertion of a thin, n+ layer at the collector junction.
    Semiconductor Science and Technology 01/2004; 19(9):1131-1137. · 1.92 Impact Factor
  • K.P. Roenker, R. Flenniken, P.B. Kosel
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    ABSTRACT: This paper describes the organization and operation of an introductory, dual level (senior/graduate) laboratory course on semiconductor device processing that is based on the fabrication and testing of GaAs MESFETs. The course is organized into a weekly lecture with a corresponding laboratory session. Over the period of one quarter, the students are led through a four mask process for fabricating n-channel GaAs MESFETs. The last three weeks of the course are utilized to perform electrical characterization of the devices and test structures incorporated in the test chip. This paper provides a description of the breakdown of the fabrication process in weekly increments, the topics covered in the accompanying lecture, resource materials provided to the student, methods used for student assessment, facilities and staffing requirements, and student capacity.
    University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial; 01/2003
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    D Todorova, N Mathur, K.P Roenker
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    ABSTRACT: Device modeling using a commercial numerical simulator has been employed for design of SiGe heterojunction bipolar transistors for high frequency, high power applications. In this study, the effects of the design of the epitaxial layer structure on power gain at X-band (10 GHz) were investigated. In particular, the base doping and width, the germanium concentration, profile and width, and the emitter and collector doping levels were investigated. Device layout issues such as emitter finger width and spacing and transistor self-heating effects were not considered. A Gaussian profile was assumed for the base doping based on a SIMS profile and the known boron out-diffusion during epitaxy. Device simulations were found to show that displacement of the collector p–n junction from its corresponding SiGe/Si heterojunction, such as arising from boron out-diffusion from the base, was found to contribute to the formation of a parasitic barrier in the conduction energy band that produced a degradation in power gain and device performance. A similar, but smaller parasitic barrier was also found to form at the emitter–base junction as a result of p–n junction displacement. The device performance was also investigated as a function of the displacement of the peak base doping from the center of the SiGe base. The simulation results show that the device can achieve significant power gain at X-band frequencies, but that the device performance achieved in practice is likely to be a sensitive function of the exact boron doping profile in the base and the extent, if any, of the displacement of the emitter and collector p–n junctions from the SiGe/Si heterojunctions at the ends of the base.
    Solid-State Electronics 01/2002; · 1.48 Impact Factor
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    A. Breed, K. P Roenker, D Todorova
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    ABSTRACT: The formation and characteristics of a parasitic conduction band barrier located at a SiGe/Si heterojunction have been investigated using a commercial numerical simulator and a simple, three-region model of a heterojunction with a nearby p–n junction. The barrier’s formation is examined as a function of the displacement of the p–n junction from the heterojunction, but also found to depend on the germanium concentration, junction doping and the applied bias. The phenomenon is of interest for understanding the performance of SiGe/Si heterojunction bipolar transistors, where the p–n junction is intentionally displaced from the heterojunction at either the emitter or collector junctions or where boron outdiffusion from the base produces p–n junction displacement. The barrier is found to scale with the germanium mole fraction and to be significantly larger when the heterojunction is displaced into the p-side of the p–n junction. Beyond some minimum separation of the junctions, the barrier height rises with junction displacement and saturates. For a given displacement, the barrier’s height can be suppressed with reverse bias or enhanced by forward bias of the p–n junction. The results of the numerical simulations are compared with those from a simple analytical model as an aid in understanding the barrier’s formation and characteristics.
    Solid-State Electronics 01/2002; 46(12):2199-2208. · 1.48 Impact Factor
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    S.P. Murray, K.P. Roenker
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    ABSTRACT: An improved analytical model for simulating the performance of SiC MESFETs has been developed for use in device design for high frequency, high power applications. The model is based on a two-dimensional analysis of the charge distribution under the gate and incorporates a field-dependent mobility, velocity saturation and charge buildup in the channel. The model is used to generate the large signal current-voltage characteristics of the device and transconductance, output conductance and capacitances for a small signal model
    Semiconductor Device Research Symposium, 2001 International; 02/2001
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    K.P. Roenker, D. Todorova, A. Breed
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    ABSTRACT: The effects of displacement of a pn junction from its corresponding SiGe/Si heterojunction have been investigated using a simple analytical model. The phenomenon is of interest for understanding the degradation in the performance of SiGe/Si heterojunction bipolar transistors when there is boron outdiffusion from the base that can produce pn junction displacement at both the emitter and collector-base junctions. This analysis describes the formation of parasitic barriers in the conduction band and their dependence on the device structure, pn junction displacement and bias. The barrier is found to be significantly larger when the heterojunction is displaced into the p-side of the pn junction
    Semiconductor Device Research Symposium, 2001 International; 02/2001
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    N. Mathur, D. Todorova, K.P. Roenker
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    ABSTRACT: The effects of displacement of the p-n junction with respect to the SiGe-Si heterojunction at both the emitter and collector junctions have been studied using a commercial numerical device simulator. Parasitic barrier formation at both junctions has been quantified and their degrading effects on HBT performance investigated as a function of junction displacement and bias. The effectiveness of changes in the device's structure, such as the insertion of an n+ launcher layer at the collector junction, has been investigated in order to reduce device sensitivity to p-n junction displacement while maintaining device performance
    Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers. 2001 Topical Meeting on; 02/2001
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    D. Todorova, N. Mathur, K.P. Roenker
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    ABSTRACT: Device modeling using a commercial numerical simulator has been employed for SiGe heterojunction bipolar transistor (HBT) device design for high frequency (10 GHz), high power applications. In this study, the effects of the design of the epitaxial layer structure on power gain at 10 GHz were investigated. In particular, the base doping and width, the Germanium concentration, profile and width, and the collector doping were investigated. Device layout and self-heating effects were not considered. The device performance was also investigated as a function of the displacement of the collector p-n junction from its SiGe/Si heterojunction and the associated formation of a parasitic barrier in the conduction energy band
    Semiconductor Device Research Symposium, 2001 International; 02/2001