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Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011; 01/2011
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IEEE Trans. VLSI Syst. 01/2010; 18:1173-1184.
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IEEE Trans. Mob. Comput. 01/2009; 8:528-543.
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VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009; 01/2009
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IEEE Trans. VLSI Syst. 01/2009; 17:1220-1232.
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IEEE Trans. VLSI Syst. 01/2008; 16:1413-1426.
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IEEE Trans. VLSI Syst. 01/2008; 16:714-724.
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ABSTRACT: Radiation-induced transient errors have become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability metrics. We present a novel ldquonoise impact analysisrdquo methodology to evaluate the transient error effects in static CMOS digital circuits. With both the circuit, and the transient noise abstracted in the format of matrices, the circuit-noise interaction is modeled by a series of matrix transformations. During the transformation, factors that potentially affect the propagation & capture of transient errors are modeled as matrix operations. Finally, a ldquonoise capture ratiordquo is computed as the probability of a sequential element capturing transient noise inside the combinational logics, It is used as a measure of the transient noise effects in the circuit. Comparison with SPICE simulation demonstrates that our technique can accurately, yet quickly estimate the probability of transient errors causing observable error effects. The proposed methodology will greatly facilitate the economic design of robust nanometer circuits.
IEEE Transactions on Reliability 10/2007; · 1.28 Impact Factor
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Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007; 01/2007
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ABSTRACT: With the increased popularity of wireless broadband net-works and the growing demand for multimedia applica-tions, such as streaming video and teleconferencing, there is a need to support diverse multimedia services over the wire-less medium. Recently pursued standardization efforts in IEEE 802.11e attempt to provide Quality of Service (QoS) differentiation mechanisms using two modes of medium ac-cess: polling-based and contention-based. However, there are a few limitations in the current approach with support-ing inaccurate flow reservations, varying flow requirements, and congestion in contention-based access. In this paper, we address the above limitations by dynamically associ-ating traffic flows appropriately to the two medium access modes and adjusting the duration of access in each mode. To show the effectiveness of our approach, we compare our adaptation policy with the 802.11e reference scheduler. We demonstrate that with our adaptation, the QoS of multime-dia applications, in terms of delay and throughput metrics, can be significantly improved (2-4.5x).
Wireless Networks. 01/2007; 13:511-535.
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ABSTRACT: Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle. In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into system-level power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example System-on-Chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheet-based and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently analyze the impact of process variations on SoC power. The proposed methodology combines efficient trace-based analysis, power-state based leakage modeling, and Monte Carlo sampling. The key benefit of the proposed methodology is that it captures the necessary inter-dependencies while avoiding iterative system-level simulation. Our implementation of the proposed techniques within an in-house system-level power estimation framework indicates 2-5 orders of magnitude efficiency gains, with negligible loss in accuracy, compared to direct Monte Carlo techniques that require iterative system simulation.
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on; 11/2006
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ABSTRACT: VLSI circuits are becoming increasingly susceptible to radiation-induced "single event upset (SEU)". This paper focuses on one type of SEU caused by particle strikes inside the combinational logics, called "single event transient (SET)". We study various factors affecting SET effects in CMOS digital circuits and present a static method of analyzing the circuit's SET tolerance. We also propose a heuristic cell resizing process to effectively improve the circuit SET tolerance with limited design overhead. Experimental results have shown that our analysis can accurately evaluate SET effects and the cell resizing process is able to significantly reduce the probability of SETs becoming stable errors with no timing cost and negligible area penalty
Test Conference, 2006. ITC '06. IEEE International; 11/2006
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Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006; 01/2006
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[show abstract]
[hide abstract]
ABSTRACT: Single-event-upset (SEU) has become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability analysis. In this paper, a static "noise impact analysis" methodology is developed to estimate the circuit vulnerability. First, both the circuit elements and the transient noise are abstracted in the format of matrices. Then the circuit-noise interaction is modeled by a series of matrix transformations, which jointly considers three masking effects that can potentially prevent transient noise from causing observable errors. Finally, the error-resiliency of the sequential elements is considered in determining the impact of transient noise on the circuit. Experiment results demonstrate that our technique can accurately yet quickly estimate the circuit failure rate by comparing with HSPICE simulation. The proposed methodology has greatly facilitate the economic design of robust nanometer circuit
Test Conference, 2005. Proceedings. ITC 2005. IEEE International; 12/2005
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[show abstract]
[hide abstract]
ABSTRACT: Reliability of nanometer circuits is becoming a major concern in today's VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft errors. Traditional noise analysis/avoidance and manufacturing testing are no longer sufficient to handle the dynamic interactions between various noise sources and unpredictable operational variations. Therefore, "robustness insertion" has been adopted as the supplementary approach to ensure high circuit reliability through on-line protections. However, the related design overhead is not always acceptable, especially for cost/timing-sensitive designs. In this paper, we present a novel "constraint-aware robustness insertion" methodology protect the sequential elements in digital circuits against various noise effects. Based on a configurable hardening sequential cell design and an efficient sequential cell robustness estimation technique, an optimization algorithm is developed to search for the optimal protection scheme under given timing and area constraints. Experiment results demonstrate that the proposed methodology is able to achieve a high degree of noise-tolerance while keeping the protection cost within limit.
Design Automation Conference, 2005. Proceedings. 42nd; 07/2005
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[show abstract]
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ABSTRACT: The paper investigates total end-to-end service variability issues in providing dynamic image adaptation services to wireless end users. While most existing image adaptation techniques focus on improving wireless transmission latency by adapting content-rich images to the time varying bandwidth availability of wireless networks, we have found dynamic service load variations at the server also significantly affect end-to-end service latency. We introduce a dynamic end-to-end image adaptation technique that optimizes the runtime image adaptation process so as to provide guaranteed total service latency (including both server processing latency and wireless transmission latency) with a maximized image quality. Through judicious tuning of application-layer image compression parameters, the proposed technique dynamically optimizes both the image quality and each component of service latency required for wireless image data services simultaneously depending on service variability issues existing at both server-side and network-side. Experimental results under synthetic service workloads demonstrate that our proposed dynamic end-to-end image adaptation can provide guaranteed service latency with a minimal impact on the image quality loss.
Wireless Communications and Networking Conference, 2005 IEEE; 04/2005
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IEEE Network. 01/2005; 19:14-20.
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IEEE Design & Test of Computers. 01/2005; 22:362-375.
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Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005; 01/2005
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[show abstract]
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ABSTRACT: Enabling real-time video streaming from a wireless appliance requires compute intensive video compression to be performed in real-time on the appliance before transmitting the data upstream. However, the tasks of real-time video encoding and streaming from the wireless appliances are challenging due to a) limited computational and battery resources, and b) limited and time-varying network bandwidth availability. In this paper, we present a technique for enabling real-time video compression and transmission from wireless appliances based on run-time video adaptation. We present an adaptation engine for dynamic selection of video compression parameters such that both the computational and the network bandwidth constraints are satisfied, while maximizing the end user's viewing quality. The algorithm is based on the analysis of the effect of different video compression parameters on computational and network resource usage, and the video quality. Since our approach is based on judicious selection of video compression parameters and does not require changes to the compression algorithm itself, it is applicable to a wide range of video compression standards. We have also developed an iPAQ-based end-to-end video streaming system to evaluate our approach. Experiments conducted on this test-bed indicate that our proposed technique achieves significant improvements in overall video quality under computation (up to 4×) and network bandwidth (∼3dB) constraints. We also show significant improvements in the energy efficiency as a result of adaptation.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTImedia 2005, September 22-23, 2005, New York Metropolitan Area, USA; 01/2005
