Chi-Chang Wang

National Chiao Tung University, Hsinchu, Taiwan, Taiwan

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Publications (4)6.13 Total impact

  • Chi-Chang Wang, Jiin-Chuan Wu
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    ABSTRACT: A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applications. It has low power dissipation, high operating speed, and a logic threshold voltage less sensitive to process and supply voltage variations. The proposed SSIB input buffer was realized in a 0.8-μm single-polysilicon double-metal (SPDM) CMOS technology, The measured logic threshold voltage variations due to process variations are ±24 mV for 5 V supply and ±16 mV for 3.3 V supply, respectively. Its logic threshold voltage variations due to supply voltage variation from 3.3 V to 5 V are within 10 mV. In ring oscillator configuration, the measured delay and power dissipation are 0.45 ns and 0.37 mW for 5-V supply and 0.51 ns and 0.14 mW for 3.3-V supply, respectively
    IEEE Journal of Solid-State Circuits 05/1998; · 3.06 Impact Factor
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    Chi-Chang Wang, Jiin-Chuan Wu
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    ABSTRACT: Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 kHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation. The new dual charge pump circuit was fabricated in a 3-μm p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7×4.5 mm<sup>2</sup>. For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 Ω and (2) the breakdown voltage requirement is reduced from 19.2 to 17 V
    IEEE Journal of Solid-State Circuits 07/1997; · 3.06 Impact Factor
  • Chi-Chang Wang, Jiin-Chuan Wu, Chin-Ming Huang
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    ABSTRACT: A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10" 480×(640×3) pixels color field emission display (FED) panel have been designed. Phase clocks were used to reduce the maximum operating frequency to 22.68 MHz. A class AB op amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24 V CMOS process, chip size is 7620 μm×17500 μm
    Vacuum Microelectronics Conference, 1996. IVMC'96., 9th International; 08/1996
  • Jiin-Chuan Wu, Chi-Chang Wang
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    ABSTRACT: A frame change data driving scheme (FCDDS) for ferroelectric LCD(FLCD) of matrix- addressing is developed which uses only positive voltages for the row and column waveforms to achieve bipolar driving waveforms on the FLCD pixels. Thus the required supply voltage for the driver chips is half that of the conventional driving scheme. Each scan line is addressed in only twice the switching time (tau) (minimum response time of FLC) so that this scheme is suitable for high duty ratio panels. In order to meet this bistable electro-optic effect of FLCD and zero net dc voltage across each pixel of the liquid crystal, turning on and turning off pixels are done at different time slots and frame slots. This driving scheme can be easily implemented using commercially available STN LCD drivers plus a small external circuit or by making an ASIC which is a slight modification of the STN driver. Both methods are discussed.
    Proc SPIE 03/1996;

Publication Stats

67 Citations
1 Download
6.13 Total Impact Points


  • 1996–1998
    • National Chiao Tung University
      • Department of Electronics Engineering
      Hsinchu, Taiwan, Taiwan