J.P. Xu

Publications (71)67.37 Total impact

• Article: Comparative Study of HfTa-based gate-dielectric Ge metal–oxide–semiconductor capacitors with and without AlON interlayer

  J. P. Xu, X. F. Zhang, C. X. Li, C. L. Chan, P. T. Lai
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  ABSTRACT: The electrical properties and high-field reliability of HfTa-based gate-dielectric metal–oxide–semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (∼1.1nm), and high dielectric constant (∼20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low-k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high-k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.
  Applied Physics A 04/2012; 99(1):177-180. · 1.63 Impact Factor
• Article: Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

  F. Ji, J. P. Xu, J. G. Liu, C. X. Li, P. T. Lai
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  ABSTRACT: TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N ₂ to suppress the growth of unstable GeO _x at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×10¹¹ cm ^-2  eV ) , small gate leakage current ( 8.6×10^-4 A   cm ^-2 at V _g- V _fb=1 V ), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet- N ₂ anneal can significantly suppress the growth of unstable low-k GeO _x .
  Applied Physics Letters 06/2011; · 3.84 Impact Factor
• Article: Improved Interfacial Properties of Ge MOS Capacitor With High-k Dielectric by Using TaON/GeON Dual Interlayer

  F. Ji, J.P. Xu, P.T. Lai, C.X. Li, J.G. Liu
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  ABSTRACT: Ge MOS capacitors with tri-layer gate dielectric are proposed by using GeON interlayer, TaON sandwich layer, and HfTiON high-k dielectric. Very small capacitance equivalent thickness (0.79~0.91 nm) is achieved. Experimental results show that the NO pretreated sample exhibits the best electrical properties, such as low interface-state density (5.4 × 10¹¹ cm^-2 eV^-1), low gate leakage current density (~ 3.16 × 10^-4 Acm^-2 at V_g - V_fb = 1 V) and high device reliability. All of these should be attributed to the facts that the NO nitridation could form a GeON interlayer with suitable N content and thus provide an excellent GeON/Ge interface with strong Ge-N bonds, while the TaON sandwich layer could separate Hf and Ge, thus effectively preventing the reaction between them and improving the interface quality and electrical properties of the devices.
  IEEE Electron Device Letters 03/2011; · 2.85 Impact Factor
• Article: Effects of Different Annealing Gases on Pentacene OTFT With HfLaO Gate Dielectric

  L.F. Deng, P.T. Lai, W.B. Chen, J.P. Xu, Y.R. Liu, H.W. Choi, C.M. Che
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  ABSTRACT: Pentacene organic thin-film transistors (OTFTs) with HfLaO high-κ gate dielectric were fabricated. The dielectric was prepared by a sputtering method and then annealed in N₂, NH₃, O₂, or NO at 400 °C. The carrier mobility of the NH₃-annealed OTFT could reach 0.59 cm²/V · s, which is higher than those of the other three devices. Moreover, the NH₃-annealed OTFT obtained the smallest subthreshold swing of 0.26 V/dec among them. Furthermore, 1/f noise measurement indicated that the NH₃-annealed OTFT achieved the smallest 1/f noise. All these should be attributed to the improved interface between the gate dielectric and the organic semiconductor associated with the passivation effects of the NH₃ annealing on the dielectric surface.
  IEEE Electron Device Letters 02/2011; · 2.85 Impact Factor
• Conference Proceeding: Improved performance of low-voltage pentacene OTFTs by Incorporating La to Hafinium Oxide Gate dielectric

  L.F. Deng, P.T. Lai, Q.B. Tao, H.W. Choi, J.P. Xu, W.B. Chen, C.M. Che, Y.R. Liu
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  ABSTRACT: Pentacene OTFTs with HfLaO or HfO₂ as gate dielectric were fabricated. The dielectrics were prepared by sputtering method and then annealed in NH₃ at 400 oC. The k value for the HfLaO and HfO₂ films amounted to 12.3 and 11.8 respectively. Both of the OTFTs could operate with a supply voltage of -5 V. The mobility of the OTFT with HfLaO gate dielectric was 0.688 cm²/Vs, which was much higher than that of the OTFT with HfO₂ gate dielectric. Moreover, the HfLaO-based OTFT obtained smaller sub-threshold swing, larger drive current and larger on/off current ratio than the HfO₂-baesd OTFT. The superior performance of the HfLaO-based OTFT is due to its better interfacial characteristics between the dielectric and the organic semiconductor. SEM images revealed that the pentacene film on HfLaO was more uniform and its grains were larger. C-V measurement indicated that Au-pentacene-HfLaO-Si structure displayed less hysteresis than Au-pentacene-HfO₂-Si structure.
  Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of; 01/2011
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  Available from: 144.206.159.178

  Article: Improved electrical properties of Ge metal-oxide-semiconductor capacitors with high-k HfO2 gate dielectric by using La2O3 interlayer sputtered with/without N2 ambient

  H. X. Xu, J. P. Xu, C. X. Li, P. T. Lai
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  ABSTRACT: The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.
  Applied Physics Letters 07/2010; 97(2):022903-022903-3. · 3.84 Impact Factor
• Conference Proceeding: Low-voltage polymer thin-film transistors with high-k HftiO gate dielectric annealed in NH3 or N2

  L.F. Deng, H.W. Choi, P.T. Lai, Y.R. Liu, J.P. Xu
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  ABSTRACT: OTFTs with P3HT as organic semiconductor and HfTiO as gate dielectric have been studied in this work. The HfTiO dielectric film was prepared by RF sputtering of Hf and DC sputtering of Ti at room temperature. Subsequently, the dielectric film was annealed in an NH₃ or N₂ ambient at 200°C. Then a layer of OTS was deposited by spin-coating method to improve the surface characteristics of the gate dielectric. Afterwards, P3HT was deposited by spin-coating method. The OTFTs were characterized by I-V measurement and 1/f noise measurement. The OTFT with gate dielectric annealed in NH₃ displays higher carrier mobility, smaller threshold voltage, smaller sub-threshold swing, and lower 1/f noise level than the OTFT annealed in N₂. Moreover, the HfTiO dielectric film annealed in NH₃ shows higher dielectric constant. In summary, HfTiO film annealed in NH₃ at low temperature is a promising candidate to act as the gate dielectric of high-quality low-voltage OTFTs.
  Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
• Conference Proceeding: A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric

  F. Ji, J.P. Xu, J.J. Chen, H.X. Xu, C.X. Li, P.T. Lai
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  ABSTRACT: In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
  Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
• Source

  Available from: hku.hk

  Conference Proceeding: Effects of annealing gas species on the electrical properties and reliability of Ge MOS capacitors with high-k Y2O3 gate dielectric

  C.X. Li, H.X. Xu, J.P. Xu, P.T. Lai
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  ABSTRACT: In this work, Ge MOS capacitors with Y₂O₃ gate dielectric were fabricated. The effects of annealing in N₂, NH₃ O₂ or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y₂O₃ dielectric. On the other hand, the NH₃ annealing resulted in H-related traps while the O₂ annealing suffered from extra GeO_x growth, thus both degrading the performance of the devices.
  Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
• Source

  Available from: hku.hk

  Conference Proceeding: Optimization of N content for Higk-k LaTiON gate dielectric of Ge MOS capacitor

  H.X. Xu, J.P. Xu, C.X. Li, L. Liu, P.T. Lai, C.L. Chan
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  ABSTRACT: Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La₂O₃ and Ti targets under different Ar/N₂ ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N₂ ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO_x interfacial layer between LaTiON and Ge substrate.
  Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
• Article: A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode.

  J. P. Xu, X. Xiao, P. T. Lai
  Microelectronics Reliability. 01/2010; 50:1081-1086.
• Article: Improved electrical properties of HfTiO/GeO x N y gate dielectric Ge MOS capacitors by using wet–NO Ge-surface pretreatment

  J. P. Xu, X. Zou, C. X. Li, P. T. Lai, C. L. Chan
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  ABSTRACT: Reactive cosputtering is employed to prepare high-permittivity HfTiO gate dielectric on n-Ge substrate. Effects of Ge-surface pretreatment on the interface and gate leakage properties of the dielectric are investigated. Excellent performances of Al/HfTiO/GeO x N y /n-Ge MOS capacitor with wet–NO surface pretreatment have been achieved with a interface-state density of 2.1×1011eV−1 cm−2, equivalent oxide charge of −7.67×1011cm−2 and gate leakage current density of 4.97×10−5A/cm2 at V g =1V.
  Applied Physics A 01/2009; 94(2):419-422. · 1.63 Impact Factor
• Conference Proceeding: Improved properties of Ge MOS capacitors with HfTiON or HfTiO gate dielectric by using Wet-NO Ge-surface pretreatment

  C.X. Li, X. Zou, J.P. Xu, P.T. Lai
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  ABSTRACT: HfTiO/GeO_xN_y and HfTiOn/GeO_xN_y stack gate dielectric are prepared by using wet-NO or wet-N₂O pretreatment on Ge substrate. Experimental results show that the wet NO pretreatment can lead to excellent interface properties, gate leakage properties and device reliability, especially for the HfTiON/GeO_xN_y dielectric. The involvement mechanisms lie in the roles of N in blocking oxygen diffusion and Ge out-diffusion and suitable N incorporation in the GeO_xN_y interlayer, which effectively suppress further growth of GeO_xN_y interlayer and the growth of unstable GeO_x during subsequent processing.
  Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on; 01/2009
• Conference Proceeding: Enhanced performance of Si MOS capacitors with HfTaOxNy gate dielectric by using AlOxNy or TaOxNy interlayer

  C.X. Li, X.F. Zhang, J.P. Xu, P.T. Lai
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  ABSTRACT: Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlO_xN_y or TaO_xN_y was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaO_xN_y capacitor with TaO_xN_y interlayer achieved better performance with larger capacitance and smaller leakage current than its counterpart with AlO_xN_y interlayer.
  Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on; 01/2009
• Conference Proceeding: Stability analysis and AC modeling of high-efficiency BUCK/BOOST converter

  L.L. Chen, J.P. Xu, S.N. Cheng, L. Liu, L.F. Deng
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  ABSTRACT: A linear model of voltage-controlled BUCK/BOOST converter in CCM mode is built by means of inductor-voltage averaging approximation and capacitor-current averaging approximation according to working conditions. It is shown that the closed-loop control-to-output characteristics coincide with the results derived by the state-space averaging method. Dynamic characteristic of the system is simulated by using MATLAB in order to design the compensation network. The simulated results exhibit good agreement with those by HSPICE and experiment results, indicating the validity of the model and compensation network.
  Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on; 01/2009
• Article: A study on the improved programming characteristics of flash memory with Si

  L. Liu, J. P. Xu, L. L. Chen, P. T. Lai
  Microelectronics Reliability. 01/2009; 49:912-915.
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  Available from: hku.hk

  Article: Improved Electrical Properties of Ge p-MOSFET With Gate Dielectric by Using Interlayer

  J.P. Xu, X.F. Zhang, C.X. Li, P.T. Lai, C.L. Chan
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  ABSTRACT: The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaO x N y are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaO x N y on germanium surface prior to deposition of high- k dielectrics can effectively suppress the growth of unstable GeO x , thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.
  IEEE Electron Device Letters 11/2008; · 2.85 Impact Factor
• Article: Improved electrical properties of Ge metal-oxide-semiconductor capacitor with HfTa-based gate dielectric by using TaOxNy interlayer

  X. F. Zhang, J. P. Xu, C. X. Li, P. T. Lai, C. L. Chan, J. G. Guan
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  ABSTRACT: HfTa-based oxide and oxynitride with or without Ta O _x N _y interlayer are fabricated on Ge substrate to form metal-oxide-semiconductor (MOS) capacitors. Their electrical properties and reliabilities are measured and compared. The results show that the MOS capacitor with a gate stack of HfTa-based oxynitride and thin Ta O _x N _y interlayer exhibits low interface-state/oxide-charge densities, low gate leakage, small hysteresis, small capacitance equivalent thickness (∼0.94 nm ) , and high dielectric constant (∼24) . All these should be attributed to the blocking role of the Ta O _x N _y interlayer against penetration of O into the Ge substrate and interdiffusions of Hf, Ge, and Ta, thus effectively suppressing the formation of unstable low- k Ge O _x and giving a superior Ta O _x N _y/ Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric greatly improves device reliability through the formation of strong N-related bonds.
  Applied Physics Letters 07/2008; · 3.84 Impact Factor
• Conference Proceeding: Improved Performance for OTFT with HfTiO2 as gate dielectric by N2O annealing

  W.M. Tang, K.H. Cheng, C.H. Leung, P.T. Lai, J.P. Xu, C.M. Che
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  ABSTRACT: OTFTs with HfTiO₂ as gate dielectric have been successfully fabricated. The devices show small threshold voltage and subthreshold slope, and thus are suitable for low-voltage and low-power applications. This work also finds that OTFT with gate dielectric annealed in N₂O has larger dielectric constant, smaller threshold voltage, smaller subthreshold slope and larger on/off ratio than the N₂-annealed sample. This demonstrates that the N₂O annealing is an important surface treatment for preparing a high-quality insulator/organic interface.
  Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
• Article: A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric.

  F. Ji, J. P. Xu, P. T. Lai, J. G. Guan
  Microelectronics Reliability. 01/2008; 48:693-697.