S. Zafar

IBM, Armonk, New York, United States

Are you S. Zafar?

Claim your profile

Publications (36)30 Total impact

  • [show abstract] [hide abstract]
    ABSTRACT: In this paper, a detailed study of charge relaxation in high-k metal-gate nFETs is reported. We show that independent fast and slow relaxation occur in parallel. While the slow charge relaxation follows the typical universal dependence on trelax/tstress[1], the fast transient relaxation does not show stress time dependence for the stress time range investigated in this work (ts>;~200us). Study of the dependence on high-k thickness and electric field also reveals very different characteristics between the fast and slow BTI and suggests the fast BTI is likely caused by a specific group of defects with very short capture time near Fermi level in the high-k layer.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
  • [show abstract] [hide abstract]
    ABSTRACT: Diffusion of oxygen ions in thin (
    Applied Physics Letters 01/2011; 98. · 3.79 Impact Factor
  • [show abstract] [hide abstract]
    ABSTRACT: We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low V<sub>TH</sub>s and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.
    VLSI Technology, 2009 Symposium on; 07/2009
  • [show abstract] [hide abstract]
    ABSTRACT: The stability and performance characteristics of static random access memories (SRAMs) are known to degrade with time due to the impact of negative and positive bias temperature instabilities (NBTI (in PFET) and PBTI (in NFET)). In this work, we provide insights into relative sensitivities of these phenomena on speed and stability of SRAM cells. Relative impact on access time, stability, and tolerability of one phenomenon over another has been studied for different application specific (high-performance or low-power) SRAM cells. We show that high-performance SRAM cells should have lower VT drift due to PBTI compared with dense cells to contain read stability and access time. Further, worst-case static stress poses tighter process constraints compared with alternating stress.
    Reliability Physics Symposium, 2009 IEEE International; 05/2009
  • [show abstract] [hide abstract]
    ABSTRACT: Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under ‘worst case condition’ gets more important because of reduced guard-banding due to process induced instability. In this work, circuit insights into worst-case conditions and effect of NBTI and PBTI, individually and in combination, on the stability of an SRAM cell are presented. It is shown that measurable quantities such as static noise-margin are not sufficient to completely understand the combined effect of NBTI and PBTI. Monte-Carlo simulations are performed in a 45 nm PDSOI technology to estimate the increase in cell failure probability with time. In worst case, NBTI and PBTI both degrade read stability (significantly) and writability (marginally). Further, we analyze the choice of optimal power supply considering the trade-off between short-term stability (due to process variations) and long-term stability (due to NBTI/PBTI) to achieve six-sigma confidence in SRAM cell robustness.
    Microelectronics Reliability. 01/2009;
  • [show abstract] [hide abstract]
    ABSTRACT: In this work, we report a study of negative bias temperature instability (NBTI) recovery in high-k/metal-gate p-channel field effect transistors (pFETs) with different interfaces. New results on the dependence of recovery on interface, stressing voltage (Vs), stressing temperature and stressing time (ts) are shown.
    Microelectronic Engineering 01/2009; 86(7–9):1888-1890. · 1.22 Impact Factor
  • Source
    [show abstract] [hide abstract]
    ABSTRACT: Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest T<sub>inv</sub> (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T<sub>inv</sub> (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
  • [show abstract] [hide abstract]
    ABSTRACT: We present a systematic examination of work function modulation and scavenging effect on fully silicided gates using different NiSi alloys (Ti, Hf, Zr, Pd, Pt, and Al) as well as different phases (Ni<sub>31</sub>Si<sub>12</sub> and Ni<sub>rich</sub>-Pt-Si). It is shown that the interface layer between gate FUSI and dielectric is the key to modulate the work function. FUSI alloys were able to prevent Fermi level pining on HfSiO and HfO<sub>2</sub> by modification of the top interface. A ~400 meV work function shift was achieved toward the conduction band edge using NiAlSi demonstrating a mobility of 300 cm<sub>2</sub>/Vs at peak, matching NiSi control devices on Hf<sub>x </sub>SiO<sub>y</sub>. Interface engineering with FUSI alloy gate has not only shown threshold voltage modulation but also enabled further gate oxide scaling (0.15 ~ 0.2nm) compared to NiSi control device. Additional gate oxide scaling is due to the increase of effective dielectric constant in the FUSI gate stack. TEM, EELS, and EDX showed that work function modulation is attributed to the Al pile up at interface. Ni rich silicide FUSI gates showed a ~250mV shift from mid gap toward valence band edge with elimination of Fermi-level pining by modification of the top dielectric interface
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
  • Source
    J.H. Stathis, S. Zafar
    [show abstract] [hide abstract]
    ABSTRACT: Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted.
    Microelectronics Reliability. 01/2006;
  • [show abstract] [hide abstract]
    ABSTRACT: Threshold voltage (V<sub>t</sub>) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V <sub>t</sub> shift is an important transistor reliability issue. V<sub>t </sub> shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO<sub>2</sub> SiO<sub>2</sub>/HfO<sub>2</sub> and SiO<sub>2</sub>/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO <sub>2</sub>/NiSi and SiO<sub>2</sub>/HfO<sub>2</sub>/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO<sub>2</sub>/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO <sub>2</sub>/HfO<sub>2</sub>/TiN and SiO<sub>2</sub>/HfO<sub>2</sub>/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO<sub>2</sub> devices is much smaller than those observed for SiO<sub>2</sub>/HfO<sub>2</sub>/NiSi. In summary for SiO<sub>2</sub>/HfO<sub>2</sub> stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO<sub>2</sub> FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO<sub>2</sub>/FUSI FETs
    VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on; 01/2006
  • [show abstract] [hide abstract]
    ABSTRACT: We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm<sup>2</sup>/Vs @ 1MV/cm) at the thinnest T<sub>inv</sub> (1.4 nm) reported to date. These stacks are formed by capping HfO<sub>2</sub> with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the V<sub>t</sub>/V <sub>fb</sub> from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET V<sub>t</sub> shift are discussed
    VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on; 01/2006
  • Applied Physics Letters 08/2005; 87(5):9901-. · 3.79 Impact Factor
  • [show abstract] [hide abstract]
    ABSTRACT: We report the following results for metal/HfO<sub>2</sub>/oxide stacks, (i) The energy level band diagram of HfO<sub>2</sub>/SiO<sub>2</sub> stacks is experimentally determined for the first time; the conduction band offset between HfO<sub>2</sub> and interfacial SiO<sub>2</sub> is estimated to be 2.05 eV. (ii) Work functions of W, Re and TaSiN are measured for HfO<sub>2</sub>/SiO<sub>2</sub>/Si and SiO<sub>2</sub>/Si stacks: work functions exhibit no Fermi pinning effect in HfO<sub>2</sub>, unlike previous report by Schaeffer et al in 2004. (iii) The impact of metal gate deposition on its work function and the oxide charge density is investigated. Measurements show that the tungsten work function is independent of deposition time and method (CVD vs. sputtering). However, oxide charge density (Q<sub>0X</sub>) depends both on the deposition time and method: Q<sub>0X</sub> is positively charged for CVD and negatively charged for sputtered depositions. Also, Q<sub>0X</sub> increases with W deposition time.
    VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
  • [show abstract] [hide abstract]
    ABSTRACT: Conventional scaling is no longer effective to continue device performance trend because of technological difficulties in the scaling of key device parameters. In this paper, the authors discussed device scaling options beyond convention device structures. Recent progress in advanced gate stack, ultrathin body silicon on insulator (UTSOI) MOSFET and FinFET structures for improved electrostatic were discussed. Various mobility enhancement techniques were also discussed including strained silicon hybrid orientation technology, and Ge FET.
    Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on; 06/2005
  • [show abstract] [hide abstract]
    ABSTRACT: Negative bias temperature instability (NBTI) causes the threshold voltage (V,) to shift with stressing time and is an increasingly important reliability issue with CMOS scaling. To continue scaling, FinFETs and FETs on hybrid orientation substrates are two new technologies that are under consideration. Recently, higher NBTI was reported for FinFETs in comparison to planar FETs and this higher NBTI was attributed to <110> orientation of the fin sidewall. In this paper, we present a systematic study of NBTI in <110> and <100> orientation pFETs with thermal SiON, plasma nitrided SiON, and thermal SiON/HfO<sub>2</sub> as gate dielectrics. The objective of the study is to compare NBTI in pFETs as a function of substrate orientation and gate dielectric films and to apply a recently proposed physics based model to the NBTI data for gaining insights into NBTI. Three main results are reported. (I) Measurements show that the NBTI is larger for <110> orientation in comparison to <100> for the thermal SiON and SiON/HfO<sub>2</sub> pFETs. In contrast, NBTI is independent of substrate orientation for the plasma nitrided SiON pFETs. (II) NBTI induced increase in positive charge density is larger for the plasma nitrided SiON pFETs in comparison to those for thermal SiON and SiON/HfO<sub>2</sub> pFETs. (III) The model provides good fits to V, shift versus stressing time data for various pFETs. Using the model fits, V<sub>t</sub> shifts after 10 years stressing are estimated and compared for various pFETs. Model parameters attribute the enhanced NBTI in <110> orientation pFETS to higher bonded hydrogen densities at the oxide/Si interface for the case of thermal SiON and SiON/HfO<sub>2</sub> pFETs. Since model fitting parameters are independent of substrate orientation for pFETS with plasma nitrided SiON. a possible explanation is that the incorporation of bonded hydrogen at the silicon interface is determined predominantly by the plasma nitridation conditions.
    VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
  • [show abstract] [hide abstract]
    ABSTRACT: We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.
    VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
  • [show abstract] [hide abstract]
    ABSTRACT: Over recent years, there has been increasing research and development efforts to replace SiO<sub>2</sub> with high dielectric constant (high-κ) materials such as HfO<sub>2</sub>, HfSiO, and Al<sub>2</sub>O<sub>3</sub>. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-κ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.
    IEEE Transactions on Device and Materials Reliability 04/2005; · 1.52 Impact Factor
  • [show abstract] [hide abstract]
    ABSTRACT: Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.
    IEEE Transactions on Electron Devices 02/2005; · 2.06 Impact Factor
  • [show abstract] [hide abstract]
    ABSTRACT: A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T<sub>inv</sub>, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO<sub>2</sub>, HfO<sub>2</sub>:N, HfSiO, HfSiON, ZrO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub>); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
  • [show abstract] [hide abstract]
    ABSTRACT: Electron mobilities of W/HfO<sub>2</sub> stacks were found to increase monotonically with annealing temperature with little (peak) or no degradation (1 MV/cm) when compared to poly-Si devices using conventional oxides. For stacks annealed at high temperature charge pumping curves indicate low interface states densities of ∼5 × 10<sup>10</sup> charges/cm<sup>2</sup>. Mobility enhancement can also be attributed to a structural change in the HfO<sub>2</sub> gate stack rather than due to only interfacial layer re-growth.
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005