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S. Inaba,
K. Okano,
S. Matsuda,
M. Fujiwara,
A. Hokazono,
K. Adachi,
K. Ohuchi,
H. Suto,
H. Fukui,
T. Shimizu, [......],
T. Kudo,
H. Shibata,
S. Taniguchi,
M. Takayanagi,
A. Azuma,
H. Oyamatsu,
K. Suguro,
Y. Katsumata,
Y. Toyoshima,
H. Ishiuchi
[show abstract]
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ABSTRACT: The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I<sub>g</sub> and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 μA/μm in nFET and 272 μA/μm in pFET at V<sub>dd</sub>=0.85 V (at I<sub>off</sub>=100 nA/μm) were achieved and they are the best values for 35 nm gate length CMOS reported to date.
IEEE Transactions on Electron Devices 01/2003; · 2.32 Impact Factor
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S Inaba,
K Okano,
S Matsuda,
M Fujiwara,
A. Hokazono,
K Adachi,
K Ohuchi,
H Suto,
H Fukui,
T Shimizu, [......],
T Matsushita,
S. Magoshi,
Y Watanabe,
M Takayanagi,
A Azuma,
H. Oyamatsu,
K. Suguro,
Y Katsumata,
Y. Toyoshima,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 μA/μm in nFET and 272 μA/μm in pFET at V<sub>dd</sub> = 0.85 V (I<sub>off</sub> = 100 nA/μm) were achieved, which are the best values in 35 nm gate length CMOS reported to date
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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[show abstract]
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ABSTRACT: The mechanism of gate depletion in PMOS W polymetal (W/WN<sub>x
</sub>/poly-Si) gate was investigated. It was found for the first time
that the pile-up of boron (B) occurred at the WN<sub>x</sub>/poly-Si
interface due to B-N formation and the B concentration in poly-Si
decreased resulting in gate depletion. In order to prevent the B
pile-up, we developed a new process module and succeeded in suppressing
the gate depletion without B penetration into Si substrate by using a
thin amorphous Si buffer (ASB) layer combined with miniaturization of
poly-Si grain-size
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
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[show abstract]
[hide abstract]
ABSTRACT: Damascene metal gate MOSFETs with Co silicided source/drain and
high-k dielectrics were successfully formed without agglomeration of
CoSi<sub>2</sub> films. Good transistor characteristics were
reproducibly obtained and shorter inverter delay was confirmed by 151
stage CMOS ring oscillators
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
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ABSTRACT: Anomalously high parasitic resistance is observed when SiN gate
sidewall spacer is incorporated into sub-0.25-μm pMOSFET's. The
parasitic resistance in p<sup>+</sup> S/D extension region increases
remarkably by decreasing BF<sub>2</sub> ion implantation energy to lower
than 10 keV. It is confirmed that low activation efficiency of boron in
p<sup>+</sup> extension is the reason for such high parasitic
resistance. The reduction of activation efficiency of boron may result
from hydrogen passivation of boron acceptor; Fourier transform infrared
absorption (FT-IR) measurement suggests that diffused hydrogen from SIN
into p<sup>+</sup> extension region forms the silicon-hydrogen-boron
complex. It is also found that the activation efficiency of boron
correlates well both with implantation energy of BF<sub>2</sub> and the
amorphization rate of substrate. Therefore, in sub-0.25-μm era, the
extra amorphization step is essential not only to form a shallow
junction but also to enhance boron activation. Germanium
preamorphization implantation (Ge PAI) is hence applied to p<sup>+</sup>
extension of 0.15 μm pMOSFET's. It is finally demonstrated that this
Ge PAI process reduces the total parasitic resistance to improve the
drain saturation current by up to 10%
IEEE Transactions on Electron Devices 07/1999; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: With decreasing implantation energy of BF<sub>2</sub> lower than 10 keV, anomalously low activation efficiency as low as 15% in p+ source/drain extension of pMOSFETs is observed when SiN gate sidewalls are used. It is demonstrated that hydrogen from the SiN film diffuses into the p+ extension, and passivates boron acceptor. Significant decrease of activation efficiency with reducing BF<sub>2</sub> implantation energy indicates that decrease of amorphization rate at the extension implantation is the origin of low activation efficiency. In sub-0.25 μm era, the extra amorphization step is indispensable to suppress hydrogen passivation of boron for achieving low parasitic resistance of pMOSFETs
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on; 07/1996
