M. Khare

Publications (48)13.9 Total impact

• Conference Proceeding: Sub-25nm FinFET with advanced fin formation and short channel effect engineering

  T. Yamashita, V.S. Basker, T. Standaert, C.-C. Yeh, T. Yamamoto, K. Maitra, C.-H. Lin, J. Faltermeier, S. Kanakasabapathy, M. Wang, [......], M. Colburn, M. Hane, D. Mcherron, V.K. Paruchuri, B. Doris, R.J. Miller, H. Bu, M. Khare, J. O'Neill, E. Leobandung
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  ABSTRACT: FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100 nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO = 3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.
  VLSI Technology (VLSIT), 2011 Symposium on; 07/2011
• Conference Proceeding: ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

  K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, B. Haran, A. Kumar, T. Adam, A. Reznicek, N. Loubet, H. He, [......], T. Wu, H. Bu, V. Paruchuri, D. Sadana, V. Narayanan, W. Haensch, J. O'Neill, T. Hook, M. Khare, B. Doris
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  ABSTRACT: For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at Ioff = 100 nA/μm for high performance (HP) and 920/880 μA/μm at Ioff = 1 nA/μm for low power (LP), respectively, at VDD = 1 V. High density 6-T SRAM cells down to 0.08 μm2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive LG scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.
  VLSI Technology (VLSIT), 2011 Symposium onVLSI Technology (VLSIT), 2011 Symposium on; 01/2011
• Conference Proceeding: Full metal gate with borderless contact for 14 nm and beyond

  S. Seo, L.F. Edge, S. Kanakasabapathy, M. Frank, A. Inada, L. Adam, M.M. Wang, K. Watanabe, P. Jamison, K. Ariyoshi, [......], S.L. Brown, J. Chang, E.A. Cartier, D. Park, J.H. Stathis, B. Doris, R. Divakaruni, M. Khare, V. Narayanan, V.K. Paruchuri
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  ABSTRACT: Tungsten-based full metal gate (FMG) stacks that are equivalent to or better than metal-inserted poly-Si (MIPS) stack have been developed. These fully encapsulated FMG stacks enable borderless source/drain contacts needed for the 14 nm technology node and beyond, where the contacted gate pitch is expected to be less than 80 nm. Tungsten replaces gate salicidation with the sheet resistance ≤ 14 Ω/□. FMG stack show excellent Tinv scaling (0.92 and 1.15 nm for NFET and PFET, respectively) and enhanced hole mobility by 20% compared to MIPS gate stack. Fully integrated short channel devices and borderless contacts are demonstrated at 80 nm contacted gate pitch.
  VLSI Technology (VLSIT), 2011 Symposium onVLSI Technology (VLSIT), 2011 Symposium on; 01/2011
• Conference Proceeding: A viable and comprehensive TDDB assessment methodology for investigation of SRAM Vmin failure

  E. Wu, G. Braceras, D. Turner, A. Swift, M. Johnson, J. Sue, S. Tous, B. Li, R. Bolam, G. Massey, M. Khare
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  ABSTRACT: Based on fundamental understanding of oxide breakdown (BD) physics established for thin oxides, we demonstrate that product circuit malfunction such as SRAM V_min failure due to intrinsic TDDB can be accurately predicted. This prediction is based on a viable methodology using power-law voltage acceleration and progressive BD.
  Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
• Conference Proceeding: Scaling of 32nm low power SRAM with high-K metal gate

  H.S. Yang, R. Wong, R. Hasumi, Y. Gao, N.S. Kim, D.H. Lee, S. Badrudduza, D. Nair, M. Ostermayr, H. Kang, [......], S. Samavedam, D. Jaeger, C.V. Baiocco, M. Sherony, M. Khare, C. Lage, J. Pape, J. Sudijono, A.L. Steegen, S. Stiffler
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  ABSTRACT: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum² and 0.124 mum². SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T_inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum² cell to meet low power application requirements.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: 32nm general purpose bulk CMOS technology for high performance applications at low voltage

  F. Arnaud, J. Liu, Y.M. Lee, K.Y. Lim, S. Kohler, J. Chen, B.K. Moon, C.W. Lai, M. Lipinski, L. Sang, [......], D.V. Coolbaugh, H.W. Kim, Y.C. Ee, J. Sudijono, A. Thean, M. Sherony, S. Samavedam, M. Khare, C. Goldberg, A. Steegen
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  ABSTRACT: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A_VT) improvement (A_VT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um² SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

  K. Henson, H. Bu, M.H. Na, Y. Liang, U. Kwon, S. Krishnan, J. Schaeffer, R. Jha, N. Moumen, R. Carter, [......], R. Knarr, T. Bailey, B. Zhang, K. Wong, T. Graves-Abe, E. Luckowski, D.-G. Park, V. Narayanan, M. Chudzik, M. Khare
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  ABSTRACT: CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond

  Xinlin Wang, G. Shahidi, P. Oldiges, M. Khare
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  ABSTRACT: In this work, two different methodologies are used to quantitatively evaluate devices with metal high-k gate dielectrics for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band edge work function for the metal gate offers potential benefits for device scaling over conventional polysilicon gates for high performance (HP) application at the 32 nm CMOS technology node and beyond.
  Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on; 10/2008
• Conference Proceeding: A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

  X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M. Zaleski, H.S. Yang, [......], S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J. Sudijono, R. Lindsay, J.H. Ku, M. Khare, A. Steegen
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  ABSTRACT: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum². Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V V_dd with a low cost process. With this high performance transistor, V_dd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L_gate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.
  VLSI Technology, 2008 Symposium on; 07/2008
• Conference Proceeding: Extendibility of NiPt silicide to the 22-nm node CMOS technology

  K. Ohuchi, C. Lavoie, C.E. Murray, C.P. D'Emic, I. Lauer, J.O. Chu, Bin Yang, P. Besser, L.M. Gignac, J. Bruley, [......], A.W. Topol, M.J. Rooks, J.J. Bucchignano, V. Narayanan, M. Khare, M. Takayanagi, K. Ishimaru, Dae-Gyu Park, G. Shahidi, P.M. Solomon
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  ABSTRACT: This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10^-8 Omega-cm² for both n⁺ and p⁺ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.
  Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on; 06/2008
• Conference Proceeding: (110) channel, SiON gate-dielectric PMOS with record high I on =1 mA/¿m through channel stress and source drain external resistance (R ext ) engineering

  B Yang, A Waite, H Yin, J Yu, L. Black, D. Chidambarrao, A. Domenicucci, X Wang, S.H. Ku, Y Wang, [......], D Park, C. Sung, R. Wachnik, G. Freeman, D. Schepis, E. Maciejewski, M. Khare, E. Leobandung, S. Luning, P. Agnello
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  ABSTRACT: This paper presents for the first time (110) PMOS characteristics without R_ext degradation, allowing investigation of fundamental mobility and demonstration of drive current I_on in excess of 1mA/mum at I_off =100 nA/mum.
  Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
• Conference Proceeding: Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

  K. Ohuchi, C. Lavoie, C. Murray, C. D'Emic, J.O. Chu, Bin Yang, P. Besser, L. Gignac, J. Bruley, G.U. Singco, [......], A.W. Topol, M.J. Rooks, J.J. Bucchignano, V. Narayanan, M. Khare, M. Takayanagi, K. Ishimaru, Dae-Gyu Park, G. Shahidi, P. Solomon
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  ABSTRACT: This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10^-8 Omega-cm² for both n⁺ and p⁺ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.
  Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
• Conference Proceeding: Scalability of Direct Silicon Bonded (DSB) Technology for 32nm Node and Beyond

  Haizhou Yin, C.Y. Sung, K.L. Saenger, M. Hamaguchr, R. Hasumi, K. Ohuchr, H. Ng, R. Zhang, K.J. Stein, T.A. Wallner, [......], G. Pfeiffer, R. Klemhenz, R. Bendernagel, D.K. Sadana, M. Takayanagi, K. Ishimaru, S.W. Crowder, D. Park, M. Khare, G. Shahidi
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  ABSTRACT: When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007
• Conference Proceeding: Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

  B.F. Yang, K. Nummy, A. Waite, L. Black, H. Gossmann, H. Yin, Y. Liu, B. Kim, S. Narasimha, P. Fisher, [......], C. Sheraw, D. Wehella-gamage, J. Holt, X. Chen, D. Park, C.Y. Sung, D. Schepis, M. Khare, S. Luning, P. Agnello
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  ABSTRACT: This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong channel drives with I_on=800 muA/mum at I_off=100 nA/mum (V_dd=10 V) for 190 nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total I_on degradation than (100) PMOS when poly-pitch scales from 250 nm to 190 nm.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007
• Source

  Available from: co.uk

  Conference Proceeding: High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

  M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, C. Dewan, D. Park, H. Bu, W. Natzle, W. Yan, [......], S. Zafar, T. Ando, R. Iijima, M. Takayanagi, V. Narayanan, R. Wise, Y. Zhang, R. Divakaruni, M. Khare, T.C. Chen
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  ABSTRACT: Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest T_inv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T_inv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007
• Conference Proceeding: CMOS Fabricated by Hybrid-Orientation Technology (HOT)

  Bin Yang, M Yang, D.M. Fried, C. D. Sheraw, A Waite, K. Nummy, L. Black, S.D. Kim, H Yin, B Kim, S. Narasimha, X Chen, M. Khare, S. Luning, P. Agnello
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  ABSTRACT: Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence, as well as the high Rext issue for (110) PMOS are discussed in this paper.
  Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on; 07/2007
• Source

  Available from: psu.edu

  Article: Optimization of silicon technology for the IBM System z9

  D. J. Poindexter, S. R. Stiffler, P. T. Wu, P. D. Agnello, T. Ivers, S. Narasimha, T. B. Faure, J. H. Rankin, D. A. Grosch, M. D. Knox, D. C. Edelstein, M. Khare, G. B. Bronner, H.-J. Nam, S. A. Butt
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  ABSTRACT: IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9™ processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9™ to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.
  Ibm Journal of Research and Development 02/2007; · 0.72 Impact Factor
• Conference Proceeding: Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS

  Haizhou Yin, C.Y. Sung, H. Ng, K.L. Saenger, V. Chan, S. Crowder, R. Zhang, J. Li, J.A. Ott, G. Pfeiffer, [......], K. Cheng, A. Mesfin, R. Kelly, V. Ku, Z.J. Luo, N. Rovedo, K. Fogel, D.K. Sadana, M. Khare, G. Shahidi
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  ABSTRACT: Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in 65nm node and eDRAM in 90nm node have been demonstrated on DSB using the SPE-before-STI scheme
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Source

  Available from: Werner Rausch

  Conference Proceeding: High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

  S. Narasimha, K. Onishi, H.M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, [......], Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello
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  ABSTRACT: We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum², and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Conference Proceeding: Challenges and Opportunities for High Performance 32 nm CMOS Technology

  J. W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, D. Sadana, C.Y. Sung, W. Haensch, M. Khare
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  ABSTRACT: Starting with the 45 nm node, a tradeoff between performance and density exists that become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch" approach is demonstrated to show up to a 15% improvement over conventional layout in ring oscillators. The lower parasitics of SOI provide an additional degree of freedom allowing relaxed pitch designs to enhance performance in critical paths. Simpler device isolation in SOI is also shown to be very beneficial in this generation leading to an improved cost/performance tradeoff compared to previous generations
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007