Joohwa Kim

University of California, San Diego, San Diego, California, United States

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Publications (18)21.24 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for $Q$- and $W$-bands and a push–pull amplifier is investigated at $Q$ -band. The $Q$ -band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The $W$-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process.
    IEEE Transactions on Microwave Theory and Techniques 01/2012; 60(6):1870-1877. · 2.23 Impact Factor
  • Joohwa Kim, James F. Buckwalter
    J. Solid-State Circuits. 01/2012; 47:368-380.
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A fully-integrated $Q$-band (40–45 GHz) bidirectional transceiver is demonstrated in a 0.12-$\mu{\hbox{m}}$ SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-${\hbox{dB}}$ bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-${\hbox{dB}}$ bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is $-$ 5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm$\times $ 0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS process.
    IEEE Journal of Solid-State Circuits 01/2012; 47(2):368-380. · 3.06 Impact Factor
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    ABSTRACT: This letter demonstrates a low-power, Q-band, direct-conversion I/Q modulator. The modulator consumes 9 mW power from a 1 V supply and delivers - 9.3 dBm RF power at 39 GHz. The modulator exhibits an EVM of 5.3% for 16QAM at 3 Msymbols/s. The circuit is fabricated in 0.12 μm SiGe BiCMOS process and occupies an area of 1.5 mm2.
    IEEE Microwave and Wireless Components Letters 01/2012; 22(6):327-329. · 1.78 Impact Factor
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2$\,{\rm V}_{\rm PP}$ and 4$\,{\rm V}_{\rm PP}$, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB $\cdot\Omega$ of transimpedance over 30 GHz. The group-delay variation is ${\pm} $3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 ${\hbox{pA}}/\sqrt{\hbox{Hz}}$ . The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 $\Omega$ /pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process.
    IEEE Journal of Solid-State Circuits 01/2012; 47(3):615-626. · 3.06 Impact Factor
  • Joohwa Kim, J.F. Buckwalter
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    ABSTRACT: A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-μm SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under ±6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 mm<sup>2</sup> including the pads and consumes 73 mW from a 2-V supply.
    IEEE Journal of Solid-State Circuits 06/2011; · 3.06 Impact Factor
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    ABSTRACT: A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high drain supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450×500 µm 2 including pads, while achieving a maximum power-added-efficiency (PAE) above 20 %.
    01/2011;
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    ABSTRACT: A 5-Gb/s fully-integrated optical duobinary transceiver front-end is demonstrated in a 130-nm silicon-on-insulator (SOI) CMOS technology. A photonic microring modulator is shown to support 5 Gb/s modulation through the use of duobinary electronic modulation. Duobinary modulation is proposed to mitigate opto-electronic bandwidth limitations for the photonic ring modulator. The circuit illustrates an NRZ data eye of 500 μW amplitude and consumes 115 mW of power for both the analog and digital portions of the transmitter.
    2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011; 01/2011
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A low-power cascode distributed amplifier is demon- strated in a 45 nm silicon-on-insulator (SOI) CMOS process. The amplifier achieves a 3 dB bandwidth of 92 GHz. The peak gain is 9 dB with a gain-ripple of less 1.5 dB over the 3 dB bandwidth. The group-delay variation is under over the 3 dB bandwidth. Theamplifierconsumes73.5mWfroma1.2Vsupplyandresultsin a gain-bandwidth efficiency figure of merit of 3.53 GHz/mW. The chip occupies an area of 0.45 including the pads. Index Terms—CMOS, distributed amplifier (DA), mil- limeter-wave integrated circuit, silicon-on-insulator (SOI).
    IEEE Microwave and Wireless Components Letters 01/2011; 21(6):329-331. · 1.78 Impact Factor
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    ABSTRACT: An efficient power amplifier (PA) is demonstrated in a 0.12-μm silicon germanium (SiGe) BiCMOS process at 45 GHz. The amplifier is a single stage common-emitter amplifier (CE). The voltage handling capability of the amplifier is extended by a low impedance biasing network. The amplifier achieves a peak power-added efficiency (PAE) of 25 % at an output power of 13 dBm in linear operation and 31% in class B mode at an output power of 13.3 dBm. The maximum saturated output power Psat is 14.8 dBm, at which the circuit consumes 77 mW. The chip occupies an area of 0.27 mm2 including pads.
    Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE; 01/2011
  • J.F. Buckwalter, Joohwa Kim
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    ABSTRACT: A high-frequency amplifier technique is introduced based on traveling-wave amplification. As opposed to distributing amplifiers to support traveling waves, the proposed technique amplifies forward traveling waves while attenuating backward traveling waves through a cascade of stages that share a single transmission line. The behavior of the cascaded constructive wave amplifier is analyzed in terms of gain, bandwidth, stability, and noise figure. The amplifier is demonstrated in a 0.12-?? m SiGe BiCMOS process with 12 cascaded amplification stages and achieves more than 26 dB of gain at 99 GHz with a 3-dB bandwidth of 13 GHz. The input and output return loss is better than 15 and 12 dB, respectively. The noise figure of the amplifier is 10.8 dB at 85 GHz. The output-referred P 1 dB is -0.1 dBm and the amplifier consumes 113 mW, including current biasing.
    IEEE Transactions on Microwave Theory and Techniques 04/2010; · 2.23 Impact Factor
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45 nm silicon on insulator (SOI) CMOS technology. A modulator driver uses floating body devices to realize voltage swing of 2 V<sub>PP</sub> with a small-signal gain of 7.6 dB over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55-dB·Ω of transimpedance over 30 GHz. The group-delay variation is ±3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.47 pA/√Hz. The TIA consumes 9 mW from a 1 V supply for a transimpedance figure of merit of 1874.5 Ω/pJ. To the author's knowledge, this represents the lowest power consumption for a transmitter and receiver operating at 40-Gb/s in a CMOS process.
    IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A W-band, cascaded constructive wave amplifier realizes high gain and bandwidth in a 0.12 μm SiGe BiCMOS process. The amplifier achieves 37.5 dB gain at 90 GHz with a 3 dB bandwidth of 14.6 GHz. Consequently, this amplifier demonstrates a gain-bandwidth product as high as 1,095 GHz. At nominal bias condition, input and output return losses are better than 11 dB over the entire 3 dB bandwidth and the output-referred P1 dB is -5.5 dBm. The amplifier consumes 65 mW from a 1.8 V at a nominal bias condition and 130 mW from a 2 V at a high-gain bias condition. The chip occupies an area of 0.39 mm2 including the pads.
    IEEE Microwave and Wireless Components Letters 01/2010; 20(11):625-627. · 1.78 Impact Factor
  • Joohwa Kim, James F. Buckwalter
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    ABSTRACT: A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2010; 57(8):1964-1972. · 2.24 Impact Factor
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    ABSTRACT: A W-band, bidirectional constructive wave amplifier is proposed that eliminates the need for a T/R switch. The amplifier allows amplification of either a forward or backward traveling wave. The measured amplifier has a peak gain of 16 dB and bandwidth of 14.5 GHz at 90 GHz and the center frequency can be electronically controlled between 77 and 90 GHz. The circuit is fabricated in a 0.12 μm SiGe BiCMOS process, occupies an area of 0.47 mm<sup>2</sup>, and consumes approximately 32 mA from a 2 V supply. To the author's knowledge, this is the first W-band, bidirectional amplifier in a silicon/silicon-germanium process.
    IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
  • Joohwa Kim, James F. Buckwalter
    [Show abstract] [Hide abstract]
    ABSTRACT: A fully integrated Q-band (40~45 GHz) bidirectional transceiver is demonstrated in a 0.12-μm SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-dB bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-dB bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is -5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm×0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS processes.
    01/2010;
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    Joohwa Kim, J.F. Buckwalter
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    ABSTRACT: An ultra-wideband amplifier scheme is realized with two cascaded stages that are equalized for high-bandwidth and low gain ripple. The amplifier is implemented in a 0.12 mum SiGe BiCMOS process and achieves a 3 dB bandwidth of 102 GHz. The gain is 10 dB with less than 1.5 dB gain-ripple and group-delay variation under +/- 6 ps over the entire 3 dB bandwidth. The chip occupies an area of 0.29 mm<sup>2</sup> including the pads and consumes 73 mW from a 2 V supply.
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
  • James F. Buckwalter, Joohwa Kim
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    ABSTRACT: An amplifier topology - the cascaded constructive-wave amplifier (CCWA) - that combines features of traveling-wave and cascaded amplifiers for millimeter-wave applications is presented. The circuit is implemented in 0.12 mum SiGe BiCMOS. The HBT devices have f<sub>t</sub> of 200GHz. The chip measures 330x1000 mum<sup>2</sup> including the pads. The area of a single stage measures 160times60 mum<sup>2</sup>. Within a single stage, the shielded coplanar transmission line meanders through a length of 220 mum. This structure is area efficient and minimizes the distance between the input and output of the stage. In conclusion, the CCWA topology is based on cascaded traveling-wave stages that offer wideband gain previously unachievable in silicon technologies. The 26 dB amplifier provides 7 dB more gain than recent W-band work in 0.12 mum SiGe.
    IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009